Disable extreme code model, LSX, LASX testcases on LA32.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/abd-lasx.c: Skip LA32.
* gcc.target/loongarch/attr-model-1.c: Ditto.
* gcc.target/loongarch/attr-model-2.c: Ditto.
* gcc.target/loongarch/attr-model-3.c: Ditto.
* gcc.target/loongarch/attr-model-4.c: Ditto.
* gcc.target/loongarch/attr-model-5.c: Ditto.
* gcc.target/loongarch/bytepick_combine.c: Ditto.
* gcc.target/loongarch/const-double-zero-stx.c: Ditto.
* gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c: Ditto.
* gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c: Ditto.
* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c: Ditto.
* gcc.target/loongarch/explicit-relocs-tls-desc.c: Support LA32.
* gcc.target/loongarch/larch-builtin.c: Ditto.
* gcc.target/loongarch/mov-zero-2.c: Ditto.
* gcc.target/loongarch/tls-gd-noplt.c: Ditto.
* gcc.target/loongarch/vector/loongarch-vector.exp: Disable on LA32.
* lib/target-supports.exp: Disable on LA32.
---
gcc/testsuite/gcc.target/loongarch/abd-lasx.c | 1 +
.../gcc.target/loongarch/attr-model-1.c | 1 +
.../gcc.target/loongarch/attr-model-2.c | 1 +
.../gcc.target/loongarch/attr-model-3.c | 1 +
.../gcc.target/loongarch/attr-model-4.c | 1 +
.../gcc.target/loongarch/attr-model-5.c | 1 +
.../gcc.target/loongarch/bytepick_combine.c | 1 +
.../loongarch/const-double-zero-stx.c | 1 +
.../explicit-relocs-auto-extreme-tls-desc.c | 1 +
.../explicit-relocs-extreme-auto-tls-ld-gd.c | 1 +
.../explicit-relocs-extreme-tls-desc.c | 1 +
.../loongarch/explicit-relocs-tls-desc.c | 9 ++--
.../gcc.target/loongarch/larch-builtin.c | 42 +++++++++++++------
.../gcc.target/loongarch/mov-zero-2.c | 3 +-
.../gcc.target/loongarch/tls-gd-noplt.c | 3 +-
.../loongarch/vector/loongarch-vector.exp | 2 +-
gcc/testsuite/lib/target-supports.exp | 2 +-
17 files changed, 52 insertions(+), 20 deletions(-)
diff --git a/gcc/testsuite/gcc.target/loongarch/abd-lasx.c
b/gcc/testsuite/gcc.target/loongarch/abd-lasx.c
index 0cb639b969a..08d4ac821ae 100644
--- a/gcc/testsuite/gcc.target/loongarch/abd-lasx.c
+++ b/gcc/testsuite/gcc.target/loongarch/abd-lasx.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O3 -mlasx -fdump-rtl-expand-all" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
#define ABD(x, y) ((x - y > 0) ? (x - y) : -(x - y))
#define MAX(x, y) ((x) > (y) ? (x) : (y))
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
index 916d715b98b..d61abd599af 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mexplicit-relocs -mcmodel=normal -O2" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 2 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
index a74c795ac3e..5d5311c8e43 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mexplicit-relocs -mcmodel=extreme -O2" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 3 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-3.c
b/gcc/testsuite/gcc.target/loongarch/attr-model-3.c
index 5622d508678..72f661648f9 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-3.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mexplicit-relocs=auto -mcmodel=normal -O2" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 2 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-4.c
b/gcc/testsuite/gcc.target/loongarch/attr-model-4.c
index 482724bb974..951bf8cb5f5 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-4.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mexplicit-relocs=auto -mcmodel=extreme -O2" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 3 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
index 5f2c3ec9e44..c5420e341a3 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mexplicit-relocs=none -mcmodel=extreme -O2 -fno-pic" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,x" } } */
/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,y" } } */
/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,counter"
} } */
diff --git a/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
b/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
index 2a880829ca5..b66d8642ccd 100644
--- a/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
+++ b/gcc/testsuite/gcc.target/loongarch/bytepick_combine.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-not "slli\\.d" } } */
/* { dg-final { scan-assembler-not "srli\\.d" } } */
/* { dg-final { scan-assembler-times "bytepick\\.d" 1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
b/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
index fd1bb49ff2c..410c53e614e 100644
--- a/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
+++ b/gcc/testsuite/gcc.target/loongarch/const-double-zero-stx.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -maddr-reg-reg-cost=1" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-times {stx\..\t\$r0} 2 } } */
extern float arr_f[];
diff --git
a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c
index 0fc7a1a5117..fc8bf697868 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -fPIC -mcmodel=extreme -mexplicit-relocs=auto
-mtls-dialect=desc" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
__thread int a __attribute__((visibility("hidden")));
extern __thread int b __attribute__((visibility("default")));
diff --git
a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
index 35bd4570a9e..91eb082f97d 100644
---
a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
+++
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" }
*/
+/* { dg-skip-if "" { loongarch32*-*-* } } */
/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target tls_native } } }
*/
#include "./explicit-relocs-auto-tls-ld-gd.c"
diff --git
a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
index e9eb0d6f703..355d8418d91 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -fPIC -mexplicit-relocs -mtls-dialect=desc
-mcmodel=extreme -fno-late-combine-instructions" } */
+/* { dg-skip-if "" { loongarch32*-*-* } } */
__thread int a __attribute__((visibility("hidden")));
extern __thread int b __attribute__((visibility("default")));
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
index fed478458a3..d01937df5bb 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-tls-desc.c
@@ -7,7 +7,10 @@ extern __thread int b __attribute__((visibility("default")));
int test() { return a + b; }
/* { dg-final { scan-assembler
"pcalau12i\t\\\$r4,%desc_pc_hi20\\\(\\.LANCHOR0\\\)" { target tls_native } } }
*/
-/* { dg-final { scan-assembler
"addi.d\t\\\$r4,\\\$r4,%desc_pc_lo12\\\(\\.LANCHOR0\\\)" { target tls_native }
} } */
-/* { dg-final { scan-assembler
"ld.d\t\\\$r1,\\\$r4,%desc_ld\\\(\\.LANCHOR0\\\)" { target tls_native } } } */
+/* { dg-final { scan-assembler
"addi.d\t\\\$r4,\\\$r4,%desc_pc_lo12\\\(\\.LANCHOR0\\\)" { target { tls_native
&& loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler
"addi.w\t\\\$r4,\\\$r4,%desc_pc_lo12\\\(\\.LANCHOR0\\\)" { target { tls_native
&& loongarch32*-*-* } } } } */
+/* { dg-final { scan-assembler
"ld.d\t\\\$r1,\\\$r4,%desc_ld\\\(\\.LANCHOR0\\\)" { target { tls_native &&
loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler
"ld.w\t\\\$r1,\\\$r4,%desc_ld\\\(\\.LANCHOR0\\\)" { target { tls_native &&
loongarch32*-*-* } } } } */
/* { dg-final { scan-assembler
"jirl\t\\\$r1,\\\$r1,%desc_call\\\(\\.LANCHOR0\\\)" { target tls_native } } } */
-/* { dg-final { scan-assembler "add.d\t\\\$r12,\\\$r4,\\\$r2" { target
tls_native } } } */
+/* { dg-final { scan-assembler "add.d\t\\\$r12,\\\$r4,\\\$r2" { target {
tls_native && loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler "add.w\t\\\$r12,\\\$r4,\\\$r2" { target {
tls_native && loongarch32*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/larch-builtin.c
b/gcc/testsuite/gcc.target/loongarch/larch-builtin.c
index ca7ddb1406f..e937da269ae 100644
--- a/gcc/testsuite/gcc.target/loongarch/larch-builtin.c
+++ b/gcc/testsuite/gcc.target/loongarch/larch-builtin.c
@@ -2,39 +2,39 @@
/* { dg-do compile } */
-/* { dg-final { scan-assembler-times "test_rdtime_d:.*rdtime\\.d.*\\.size
test_rdtime_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_rdtime_d:.*rdtime\\.d.*\\.size
test_rdtime_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_rdtimeh_w:.*rdtimeh\\.w.*\\.size
test_rdtimeh_w" 1 } } */
/* { dg-final { scan-assembler-times "test_rdtimel_w:.*rdtimel\\.w.*\\.size
test_rdtimel_w" 1 } } */
/* { dg-final { scan-assembler-times "test_movfcsr2gr:.*movfcsr2gr.*\\.size
test_movfcsr2gr" 1 } } */
/* { dg-final { scan-assembler-times "test_movgr2fcsr:.*movgr2fcsr.*\\.size
test_movgr2fcsr" 1 } } */
-/* { dg-final { scan-assembler-times "test_cacop_d:.*cacop.*\\.size
test_cacop_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_cacop_d:.*cacop.*\\.size
test_cacop_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_cpucfg:.*cpucfg.*\\.size
test_cpucfg" 1 } } */
-/* { dg-final { scan-assembler-times "test_asrtle_d:.*asrtle\\.d.*\\.size
test_asrtle_d" 1 } } */
-/* { dg-final { scan-assembler-times "test_asrtgt_d:.*asrtgt\\.d.*\\.size
test_asrtgt_d" 1 } } */
-/* { dg-final { scan-assembler-times "test_lddir_d:.*lddir.*\\.size
test_lddir_d" 1 } } */
-/* { dg-final { scan-assembler-times "test_ldpte_d:.*ldpte.*\\.size
test_ldpte_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_asrtle_d:.*asrtle\\.d.*\\.size
test_asrtle_d" 1 { target { loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "test_asrtgt_d:.*asrtgt\\.d.*\\.size
test_asrtgt_d" 1 { target { loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "test_lddir_d:.*lddir.*\\.size
test_lddir_d" 1 { target { loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "test_ldpte_d:.*ldpte.*\\.size
test_ldpte_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times
"test_crc_w_b_w:.*crc\\.w\\.b\\.w.*\\.size test_crc_w_b_w" 1 } } */
/* { dg-final { scan-assembler-times
"test_crc_w_h_w:.*crc\\.w\\.h\\.w.*\\.size test_crc_w_h_w" 1 } } */
/* { dg-final { scan-assembler-times
"test_crc_w_w_w:.*crc\\.w\\.w\\.w.*\\.size test_crc_w_w_w" 1 } } */
-/* { dg-final { scan-assembler-times
"test_crc_w_d_w:.*crc\\.w\\.d\\.w.*\\.size test_crc_w_d_w" 1 } } */
+/* { dg-final { scan-assembler-times
"test_crc_w_d_w:.*crc\\.w\\.d\\.w.*\\.size test_crc_w_d_w" 1 { target {
loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times
"test_crcc_w_b_w:.*crcc\\.w\\.b\\.w.*\\.size test_crcc_w_b_w" 1 } } */
/* { dg-final { scan-assembler-times
"test_crcc_w_h_w:.*crcc\\.w\\.h\\.w.*\\.size test_crcc_w_h_w" 1 } } */
/* { dg-final { scan-assembler-times
"test_crcc_w_w_w:.*crcc\\.w\\.w\\.w.*\\.size test_crcc_w_w_w" 1 } } */
-/* { dg-final { scan-assembler-times
"test_crcc_w_d_w:.*crcc\\.w\\.d\\.w.*\\.size test_crcc_w_d_w" 1 } } */
+/* { dg-final { scan-assembler-times
"test_crcc_w_d_w:.*crcc\\.w\\.d\\.w.*\\.size test_crcc_w_d_w" 1 { target {
loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_csrrd_w:.*csrrd.*\\.size
test_csrrd_w" 1 } } */
/* { dg-final { scan-assembler-times "test_csrwr_w:.*csrwr.*\\.size
test_csrwr_w" 1 } } */
/* { dg-final { scan-assembler-times "test_csrxchg_w:.*csrxchg.*\\.size
test_csrxchg_w" 1 } } */
-/* { dg-final { scan-assembler-times "test_csrrd_d:.*csrrd.*\\.size
test_csrrd_d" 1 } } */
-/* { dg-final { scan-assembler-times "test_csrwr_d:.*csrwr.*\\.size
test_csrwr_d" 1 } } */
-/* { dg-final { scan-assembler-times "test_csrxchg_d:.*csrxchg.*\\.size
test_csrxchg_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_csrrd_d:.*csrrd.*\\.size
test_csrrd_d" 1 { target { loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "test_csrwr_d:.*csrwr.*\\.size
test_csrwr_d" 1 { target { loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times "test_csrxchg_d:.*csrxchg.*\\.size
test_csrxchg_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_iocsrrd_b:.*iocsrrd\\.b.*\\.size
test_iocsrrd_b" 1 } } */
/* { dg-final { scan-assembler-times "test_iocsrrd_h:.*iocsrrd\\.h.*\\.size
test_iocsrrd_h" 1 } } */
/* { dg-final { scan-assembler-times "test_iocsrrd_w:.*iocsrrd\\.w.*\\.size
test_iocsrrd_w" 1 } } */
-/* { dg-final { scan-assembler-times "test_iocsrrd_d:.*iocsrrd\\.d.*\\.size
test_iocsrrd_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_iocsrrd_d:.*iocsrrd\\.d.*\\.size
test_iocsrrd_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_iocsrwr_b:.*iocsrwr\\.b.*\\.size
test_iocsrwr_b" 1 } } */
/* { dg-final { scan-assembler-times "test_iocsrwr_h:.*iocsrwr\\.h.*\\.size
test_iocsrwr_h" 1 } } */
/* { dg-final { scan-assembler-times "test_iocsrwr_w:.*iocsrwr\\.w.*\\.size
test_iocsrwr_w" 1 } } */
-/* { dg-final { scan-assembler-times "test_iocsrwr_d:.*iocsrwr\\.d.*\\.size
test_iocsrwr_d" 1 } } */
+/* { dg-final { scan-assembler-times "test_iocsrwr_d:.*iocsrwr\\.d.*\\.size
test_iocsrwr_d" 1 { target { loongarch64*-*-* } } } } */
/* { dg-final { scan-assembler-times "test_dbar:.*dbar.*\\.size
test_dbar" 1 } } */
/* { dg-final { scan-assembler-times "test_ibar:.*ibar.*\\.size
test_ibar" 1 } } */
/* { dg-final { scan-assembler-times "test_syscall:.*syscall.*\\.size
test_syscall" 1 } } */
@@ -42,11 +42,13 @@
#include<larchintrin.h>
+#ifdef __loongarch64
__drdtime_t
test_rdtime_d ()
{
return __rdtime_d ();
}
+#endif
__rdtime_t
test_rdtimeh_w ()
@@ -72,11 +74,13 @@ test_movgr2fcsr (unsigned int _1)
__movgr2fcsr (1, _1);
}
+#ifdef __loongarch64
void
test_cacop_d (unsigned long int _1)
{
__cacop_d (1, _1, 1);
}
+#endif
unsigned int
test_cpucfg (unsigned int _1)
@@ -84,6 +88,7 @@ test_cpucfg (unsigned int _1)
return __cpucfg (_1);
}
+#ifdef __loongarch64
void
test_asrtle_d (long int _1, long int _2)
{
@@ -107,6 +112,7 @@ test_ldpte_d (long int _1)
{
__ldpte_d (_1, 1);
}
+#endif
int
test_crc_w_b_w (char _1, int _2)
@@ -126,11 +132,13 @@ test_crc_w_w_w (int _1, int _2)
return __crc_w_w_w (_1, _2);
}
+#ifdef __loongarch64
int
test_crc_w_d_w (long int _1, int _2)
{
return __crc_w_d_w (_1, _2);
}
+#endif
int
test_crcc_w_b_w (char _1, int _2)
@@ -150,11 +158,13 @@ test_crcc_w_w_w (int _1, int _2)
return __crcc_w_w_w (_1, _2);
}
+#ifdef __loongarch64
int
test_crcc_w_d_w (long int _1, int _2)
{
return __crcc_w_d_w (_1, _2);
}
+#endif
unsigned int
test_csrrd_w ()
@@ -174,6 +184,7 @@ test_csrxchg_w (unsigned int _1, unsigned int _2)
return __csrxchg_w (_1, _2, 1);
}
+#ifdef __loongarch64
unsigned long int
test_csrrd_d ()
{
@@ -191,6 +202,7 @@ test_csrxchg_d (unsigned long int _1, unsigned long int _2)
{
return __csrxchg_d (_1, _2, 1);
}
+#endif
unsigned char
test_iocsrrd_b (unsigned int _1)
@@ -210,11 +222,13 @@ test_iocsrrd_w (unsigned int _1)
return __iocsrrd_w (_1);
}
+#ifdef __loongarch64
unsigned long int
test_iocsrrd_d (unsigned int _1)
{
return __iocsrrd_d (_1);
}
+#endif
void
test_iocsrwr_b (unsigned char _1, unsigned int _2)
@@ -234,11 +248,13 @@ test_iocsrwr_w (unsigned int _1, unsigned int _2)
__iocsrwr_w (_1, _2);
}
+#ifdef __loongarch64
void
test_iocsrwr_d (unsigned long int _1, unsigned int _2)
{
__iocsrwr_d (_1, _2);
}
+#endif
void
test_dbar ()
diff --git a/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
b/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
index 6cb48052d0b..aeaf418f2a2 100644
--- a/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/mov-zero-2.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mno-lsx" } */
-/* { dg-final { scan-assembler-times "movgr2fr" 2 } } */
+/* { dg-final { scan-assembler-times "movgr2fr" 2 { target loongarch64*-*-* }
} } */
+/* { dg-final { scan-assembler-times "movgr2fr" 3 { target loongarch32*-*-* }
} } */
double
get_double_zero ()
diff --git a/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c
b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c
index 610262a7783..d65547b12b3 100644
--- a/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c
+++ b/gcc/testsuite/gcc.target/loongarch/tls-gd-noplt.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-O0 -fno-plt -mcmodel=normal -mtls-dialect=trad
-mexplicit-relocs -fPIC" } */
-/* { dg-final { scan-assembler
"pcalau12i\t.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)"
{ target tls_native } } } */
+/* { dg-final { scan-assembler
"pcalau12i\t.*%got_pc_hi20\\(__tls_get_addr\\)\n\tld\.d.*%got_pc_lo12\\(__tls_get_addr\\)"
{ target { tls_native && loongarch64*-*-* } } } } */
+/* { dg-final { scan-assembler
"pcaddu12i\t.*%got_pcadd_hi20\\(__tls_get_addr\\)\n\tld\.w.*%got_pcadd_lo12\\(.*\\)"
{ target { tls_native && loongarch32*-*-* } } } } */
__attribute__ ((tls_model ("global-dynamic"))) __thread int a;
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
index 9df3f290857..3cb47e3a2ac 100644
--- a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -17,7 +17,7 @@
#GCC testsuite that uses the `dg.exp' driver.
#Exit immediately if this isn't a LoongArch target.
-if ![istarget loongarch*-*-*] then {
+if ![istarget loongarch64*-*-*] then {
return
}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 67f1a3c8230..735f1ae141e 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4580,7 +4580,7 @@ proc check_effective_target_vect_int { } {
&& [check_effective_target_s390_vx])
|| ([istarget riscv*-*-*]
&& [check_effective_target_riscv_v])
- || ([istarget loongarch*-*-*]
+ || ([istarget loongarch64*-*-*]
&& [check_effective_target_loongarch_sx])
}}]
}
--
2.34.1
