On 12/19/2025 11:15 AM, Vineet Gupta wrote:
On some backends such as RISC-V shift counts are wrapped in subreg which
wasn't handled in current code. This showed up when looking at the
original submission of cond zero arith code and subregs omitted for
initial simplicity but then got lost along the way.
gcc/ChangeLog:
* ifcvt.cc (get_base_reg): Handle subreg.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond_ifcvt_opt.c: Adjust increased czero counts.
OK. Thanks for tackling this. Jeff
