This patch series adds support for the Synopsys RHX-100 series to the RISC-V GCC
backend. The RHX-100 is a dual-issue, 10-stage, in-order processor with
instruction fusion capabilities.
The series introduces:
1. A pipeline description for the RHX-100 series.
2. Fusion patterns added to riscv_macro_fusion_pair_p.
3. The TARGET_SCHED_FUSION_PRIORITY hook for improved load/store fusion.
4. Scheduler hooks and state tracking for dual-issue and fusion-aware
scheduling.
5. Instruction patterns for 32-bit multiply-add and bit-extract fusion.
The series was regtested with the generic mtune as a whole, not independently.
Luis Silva (5):
RISC-V: Add Synopsys RHX-100 series pipeline description.
RISC-V: Implement riscv_macro_fusion_pair_p for Synopsys RHX-100
series.
RISC-V: Implement TARGET_SCHED_FUSION_PRIORITY for Synopsys RHX-100
series.
RISC-V: Implement scheduling for Synopsys RHX-100 series.
RISC-V: Add instruction patterns for 32-bit multiply-add and
bit-extract fusion.
gcc/config.gcc | 2 +-
gcc/config/riscv/arcv-rhx100.md | 106 +++
gcc/config/riscv/arcv.cc | 887 ++++++++++++++++++
gcc/config/riscv/iterators.md | 2 +
gcc/config/riscv/riscv-cores.def | 1 +
gcc/config/riscv/riscv-opts.h | 1 +
gcc/config/riscv/riscv-protos.h | 10 +
gcc/config/riscv/riscv.cc | 107 ++-
gcc/config/riscv/riscv.h | 4 +
gcc/config/riscv/riscv.md | 141 ++-
gcc/config/riscv/t-riscv | 6 +
gcc/doc/riscv-mtune.texi | 2 +
.../riscv/arcv-fusion-limm-condbr.c | 12 +
.../gcc.target/riscv/arcv-fusion-madd.c | 12 +
.../gcc.target/riscv/arcv-fusion-xbfu.c | 14 +
15 files changed, 1297 insertions(+), 10 deletions(-)
create mode 100644 gcc/config/riscv/arcv-rhx100.md
create mode 100644 gcc/config/riscv/arcv.cc
create mode 100644 gcc/testsuite/gcc.target/riscv/arcv-fusion-limm-condbr.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arcv-fusion-madd.c
create mode 100644 gcc/testsuite/gcc.target/riscv/arcv-fusion-xbfu.c
--
2.34.0
