On 1/8/26 10:00 PM, Jeffrey Law wrote: > On 1/8/2026 8:28 PM, Peter Bergner wrote: >> gcc/ >> * config/riscv/riscv-cores.def (RISCV_CORE)<tt-ascalon-d8>: Add missing >> extensions via use of rva23s64 profile and adding zkr, smaia, smmpm, >> smnpm, smrnmi, smstateen, ssaia, ssstrict, svadu. >> > OK.
Pushed now. Thanks! > And I think we should just make you the de-facto maintainer for any > ascalon bits and more importantly a reviewer for anything in the risc-v > space. Seems like a good topic for next week's patchwork call. nod >> Rather than just adding the missing extensions to the already long extension >> list, which is pretty unwieldy and unreadable, I made use of the pre-existing >> rva23s64 profile and then added the other supported extensions over and above >> those included in the profile. This makes it easy for GCC developers to see >> that Ascalon is a RVA23 compliant cpu and makes it easier to maintain. For stage1, I think we could do more cleanups in this area. Like define rva23s64 in terms of rva23u64 plus the extensions above what's in rva23u64, rather than explicitly mentioning them all in both profiles. I think that could lead to less chance of cut/paste errors when enumerating the extension lists. Maybe this would be a good GCC intern task? Peter
