[PATCH v1] aarch64: Add support for `+poe2` and `+tev` options

[Srinath Parvathaneni]

This patch adds support for `+poe2` and `+tev` options
to enable the architectural extensions FEAT_POE2 and
FEAT_TEV respectively.

Regression tested on aarch64-none-elf and aarch64-linux-gnu
and found no regressions.

Ok for GCC16?

Regards,
Srinath.

gcc/ChangeLog:

        * config/aarch64/aarch64-option-extensions.def (poe2):
        New CLI extension option.
        (tev): Likewise.
        * doc/invoke.texi (poe2): Document option.
        (tev): Likewise.

 gcc/testsuite/ChangeLog:

        * lib/target-supports.exp
        (check_effective_target_aarch64_poe2_tev_support_ok): Add new target
        check.
        * gcc.target/aarch64/asm-poe2-tev.c: New test.
---
 .../aarch64/aarch64-option-extensions.def     |  4 ++++
 gcc/doc/invoke.texi                           |  4 ++++
 .../gcc.target/aarch64/asm-poe2-tev.c         | 20 +++++++++++++++++++
 gcc/testsuite/lib/target-supports.exp         | 11 ++++++++++
 4 files changed, 39 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-poe2-tev.c

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def 
b/gcc/config/aarch64/aarch64-option-extensions.def
index b5e4b062bed..64d075f068d 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -351,6 +351,10 @@ AARCH64_OPT_EXTENSION("pcdphint", PCDPHINT, (), (), (), "")
 
 AARCH64_OPT_EXTENSION("pops", PoPS, (), (), (), "")
 
+AARCH64_OPT_EXTENSION("poe2", POE2, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("tev", TEV, (), (), (), "")
+
 #undef AARCH64_OPT_FMV_EXTENSION
 #undef AARCH64_OPT_EXTENSION
 #undef AARCH64_OPT_EXTENSION_ALIAS
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 46d53705870..baba090323d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23244,6 +23244,10 @@ Enable the Checked Pointer Arithmetic instructions.
 @item sve-b16b16
 Enable the SVE non-widening brain floating-point (@code{bf16}) extension.
 This only has an effect when @code{sve2} or @code{sme2} are also enabled.
+@item poe2
+Enable the Permission Overlays Extension 2.
+@item tev
+Enable the TIndex Exception-like Vector Extension.
 
 @end table
 
diff --git a/gcc/testsuite/gcc.target/aarch64/asm-poe2-tev.c 
b/gcc/testsuite/gcc.target/aarch64/asm-poe2-tev.c
new file mode 100644
index 00000000000..535a413e700
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/asm-poe2-tev.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble { target elf } } */
+/* { dg-require-effective-target aarch64_poe2_tev_support_ok } */
+/* { dg-additional-options "-march=armv8-a+poe2+tev --save-temps" } */
+/* Ensure -march=armv8-a+poe2+tev is passed to the assembler and that
+   the test runs only when POE2/TEV are supported by the assembler. */
+
+void
+poe2_test ()
+{
+  __asm__ __volatile__ ("tchangef x0, x1\n" :::"memory");
+}
+
+void
+tev_test ()
+{
+  __asm__ __volatile__ ("texit\t" :::"memory");
+}
+
+/* { dg-final { scan-assembler {\ttchangef x0, x1} } } */
+/* { dg-final { scan-assembler {\ttexit} } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 46c9b624254..25f98556a41 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12713,6 +12713,17 @@ proc check_effective_target_aarch64_sysreg_guarding_ok 
{ } {
     }
 }
 
+proc check_effective_target_aarch64_poe2_tev_support_ok { } {
+    if { [istarget aarch64*-*-*] && [check_effective_target_elf] } {
+       return [check_no_compiler_messages aarch64_assembler object {
+           __asm__ ("tchangef x0, x1");
+           __asm__ ("texit");
+       } "-march=armv8-a+poe2+tev"]
+    } else {
+       return 0
+    }
+}
+
 proc check_effective_target_aarch64_asm_sve2p1_ok { } {
     if { [istarget aarch64*-*-*] } {
        return [check_no_compiler_messages aarch64_sve2p1_assembler object {
-- 
2.25.1