From: Pan Li <[email protected]>
This patch would like to combine the vec_duplicate + vmsle.vv to the
vmsle.vx. From example as below code. The related pattern will depend
on the cost of vec_duplicate from GR2VR. Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.
Assume we have asm code like below, GR2VR cost is 0.
Before this patch:
11 beq a3,zero,.L8
12 vsetvli a5,zero,e32,m1,ta,ma
13 vmv.v.x v2,a2
...
16 .L3:
17 vsetvli a5,a3,e32,m1,ta,ma
...
22 vmsle.vv v1,v2,v3
...
25 bne a3,zero,.L3
After this patch:
11 beq a3,zero,.L8
...
14 .L3:
15 vsetvli a5,a3,e32,m1,ta,ma
...
20 vmsle.vx v1,a2,v3
...
23 bne a3,zero,.L3
gcc/ChangeLog:
* config/riscv/predicates.md: Add ge to the swappable
cmp operator iterator.
* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Take
care of the swapped rtx code as well.
Signed-off-by: Pan Li <[email protected]>
---
gcc/config/riscv/predicates.md | 2 +-
gcc/config/riscv/riscv-v.cc | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 220a6f0830c..8022c84b114 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -612,7 +612,7 @@ (define_predicate "comparison_except_ge_operator"
(match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
(define_predicate "comparison_swappable_operator"
- (match_code "gtu,gt,geu"))
+ (match_code "gtu,gt,geu,ge"))
(define_predicate "ge_operator"
(match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 29dc3ebccd6..8d6e352aafb 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -6043,6 +6043,8 @@ get_swapped_cmp_rtx_code (rtx_code code)
return LT;
case GEU:
return LEU;
+ case GE:
+ return LE;
default:
gcc_unreachable ();
}
--
2.43.0
