Re: [PATCH 1/3] ira: Implicit uses via hard register constraints

[Jeffrey Law]

On 1/10/2026 9:11 AM, Stefan Schulze Frielinghaus wrote:

From: Stefan Schulze Frielinghaus <stefa...@gcc.gnu.org>

In ira_implicitly_set_insn_hard_regs() all potentially used registers
stemming from single register constraints are recorded.  Since hard
register constraints are pretty similar, do the same for those, too.
This requires to setup the preferred alternatives which is done via
ira_setup_alts() and also implemented for hard register constraints by
this patch.

This fixes an ICE were previously sched1 swapped the order of the
instructions

(insn 10 9 6 2 (parallel [
             (set (reg:DF 118)
                 (asm_operands:DF ("") ("={fr2}") 0 [
                         (reg:TF 121 [ a ])
                     ]
                      [
                         (asm_input:TF ("{fr1}") t.i:5)
                     ]
                      [] t.i:5))
             (clobber (reg:SI 98 ca))
         ]) "t.i":5:3 -1
      (expr_list:REG_DEAD (reg:TF 121 [ a ])
         (expr_list:REG_UNUSED (reg:SI 98 ca)
             (nil))))
...
(insn 13 6 14 2 (set (reg:DF 34 2)
         (const_double:DF 0.0 [0x0.0p+0])) "t.i":6:3 606 {*movdf_hardfloat64}
      (nil))

for the attached example.  This led to an ICE because register 34/fr2
was then live while allocating for pseudo 121.

gcc/ChangeLog:

        * ira-lives.cc (ira_implicitly_set_insn_hard_regs): Honor hard
        register constraints.
        * ira.cc (ira_setup_alts): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/powerpc/asm-hard-reg-1.c: New test.

OK

Jeff