The ZD constraint is specific to the mips prefetch instruction. It is
currently always enabled, leading to ICEs when xmipscbop is disabled.
Solved by only enabling the ZD constraint whenever xmipscbop is enabled.
This was regtested on risxcv64-linux with no regressions.
This was pre-approved by Jeff offline. Pushed.
Peter
gcc/
PR target/123092
* config/riscv/constraints.md (ZD): Disable when xmipscbop is disabled.
Signed-off-by: Peter Bergner <[email protected]>
---
gcc/config/riscv/constraints.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 85b4fdce5ee..673b05954e1 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -333,7 +333,7 @@ (define_constraint "Q"
(define_address_constraint "ZD"
"An address operand that is valid for a mips prefetch instruction"
- (match_test "riscv_prefetch_offset_address_p (op, mode)"))
+ (match_test "TARGET_XMIPSCBOP && riscv_prefetch_offset_address_p (op,
mode)"))
(define_constraint "Ou07"
"A 7-bit unsigned immediate."
--
2.34.1
