Hi Alfie, On 16/01/2026 15:55, Alfie Richards wrote: > Hi Alex and all, > > Heres the next attempt. > > Mostly its just the fixes Alex requested. But I had a new go at > the SME/SVE2 file split and went for: > > - aarch64-sve-builtins-sve2.def for any scalable SIMD intrinsic that is > enabled by an SVE2+ or SME+ extension and isn't clearly streaming mode > only. > - aarch64-sve-builtins-sme.def for any SVE2+ or SME+ instinsic that is > clearly streaming mode only. This usually means it uses the ZA or ZT > registers.
Thanks for doing this, I now see the subtle distinction going on here which your patch is trying to elucidate. I think this commit message from Richard S's r14-6179-gc1c267dfcdccd5 explains the criteria for inclusion in the two files most clearly: commit c1c267dfcdccd53af0d2b2c945794ab3b0d8683f Author: Richard Sandiford <[email protected]> Date: Tue Dec 5 10:24:02 2023 +0000 aarch64: Add support for SME2 intrinsics This patch adds support for the SME2 <arm_sme.h> intrinsics. The convention I've used is to put stuff in aarch64-sve-builtins-sme.* if it relates to ZA, ZT0, the streaming vector length, or other such SME state. Things that operate purely on predicates and vectors go in aarch64-sve-builtins-sve2.* instead. Some of these will later be picked up for SVE2p1. So I agree with the overall direction, just a few more comments inline below (sorry for all the bikeshedding). > > And similar for the MD files. > > Okay for master? > > Alfie > > gcc/ChangeLog: > > * config/aarch64/aarch64.md: Update comment. > * config/aarch64/aarch64-simd.md: Change comment to refer to > aarch64.md. > * config/aarch64/aarch64-sme.md: Likewise. > * config/aarch64/aarch64-sve.md: Likewise. > * config/aarch64/aarch64-sve2.md: Likewise. > * config/aarch64/aarch64-sve-builtins.def: Update comment. > * config/aarch64/aarch64-sve-builtins-base.def: Update to refer > to aarch64-sve-builtins.def. > * config/aarch64/aarch64-sve-builtins-sme.def: Likewise. > * config/aarch64/aarch64-sve-builtins-sve2.def: Likewise. > --- > gcc/config/aarch64/aarch64-simd.md | 18 +---------- > gcc/config/aarch64/aarch64-sme.md | 18 +---------- > .../aarch64/aarch64-sve-builtins-base.def | 18 ++--------- > .../aarch64/aarch64-sve-builtins-sme.def | 18 ++--------- > .../aarch64/aarch64-sve-builtins-sve2.def | 18 ++--------- > gcc/config/aarch64/aarch64-sve-builtins.def | 32 +++++++++---------- > gcc/config/aarch64/aarch64-sve.md | 18 +---------- > gcc/config/aarch64/aarch64-sve2.md | 20 ++---------- > gcc/config/aarch64/aarch64.md | 25 ++++++++------- > 9 files changed, 40 insertions(+), 145 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index 7a38310efce..4c059269383 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -18,23 +18,7 @@ > ;; along with GCC; see the file COPYING3. If not see > ;; <http://www.gnu.org/licenses/>. > > -;; Code organisation: > -; > -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are > -;; a little blurry. > -;; > -;; Therefore code is organised by the following rough principles: > -;; > -;; - aarch64.md: For shared parts of the architecture (such as defining > -;; registers and constants) and for instructions that operate on non-SIMD > -;; registers. > -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD > -;; registers. > -;; - aarch64-sve.md for SVE instructions that are pre SVE2. > -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible > with > -;; non-streaming mode. This usually means it uses the ZA or ZT register. > -;; - aarch64-sve2.md for any scalable SIMD instruction that either is > -;; streaming compatible, or theoretically could be later. > +;; Code organization: See block comment at the top of aarch64.md. > > ;; The following define_subst rules are used to produce patterns representing > ;; the implicit zeroing effect of 64-bit Advanced SIMD operations, in effect > diff --git a/gcc/config/aarch64/aarch64-sme.md > b/gcc/config/aarch64/aarch64-sme.md > index a2faa4b2bb7..72823e528de 100644 > --- a/gcc/config/aarch64/aarch64-sme.md > +++ b/gcc/config/aarch64/aarch64-sme.md > @@ -17,23 +17,7 @@ > ;; along with GCC; see the file COPYING3. If not see > ;; <http://www.gnu.org/licenses/>. > > -;; Code organisation: > -; > -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are > -;; a little blurry. > -;; > -;; Therefore code is organised by the following rough principles: > -;; > -;; - aarch64.md: For shared parts of the architecture (such as defining > -;; registers and constants) and for instructions that operate on non-SIMD > -;; registers. > -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD > -;; registers. > -;; - aarch64-sve.md for SVE instructions that are pre SVE2. > -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible > with > -;; non-streaming mode. This usually means it uses the ZA or ZT register. > -;; - aarch64-sve2.md for any scalable SIMD instruction that either is > -;; streaming compatible, or theoretically could be later. > +;; Code organization: See block comment at the top of aarch64.md. > > ;; The file is organised into the following sections (search for the full > ;; line): > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def > b/gcc/config/aarch64/aarch64-sve-builtins-base.def > index 0a3a7a0e144..9914e060f4d 100644 > --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def > +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def > @@ -17,22 +17,8 @@ > along with GCC; see the file COPYING3. If not see > <http://www.gnu.org/licenses/>. */ > > -/* Code organisation: > - > - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get > - a little blurry. > - > - Therefore code is organised by the following rough principles: > - > - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally > - incompatible with non-streaming mode. This usually means it uses the ZA > - or ZT register. > - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a > streaming mode > - intrinsic, but either is non-streaming compatible, or theoretically > could > - be later. > - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. > - - aarch64-sve-builtins.def for common data types and group definitions > used > - across all files. */ > +/* Code organization: See block comment at the top of > + aarch64-sve-builtins.def. */ > > #define REQUIRED_EXTENSIONS ssve (0) > DEF_SVE_FUNCTION (svabd, binary_opt_n, all_arith, mxz) > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sme.def > b/gcc/config/aarch64/aarch64-sve-builtins-sme.def > index 9f126e8647a..4feb4795287 100644 > --- a/gcc/config/aarch64/aarch64-sve-builtins-sme.def > +++ b/gcc/config/aarch64/aarch64-sve-builtins-sme.def > @@ -17,22 +17,8 @@ > along with GCC; see the file COPYING3. If not see > <http://www.gnu.org/licenses/>. */ > > -/* Code organisation: > - > - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get > - a little blurry. > - > - Therefore code is organised by the following rough principles: > - > - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally > - incompatible with non-streaming mode. This usually means it uses the ZA > - or ZT register. > - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a > streaming mode > - intrinsic, but either is non-streaming compatible, or theoretically > could > - be later. > - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. > - - aarch64-sve-builtins.def for common data types and group definitions > used > - across all files. */ > +/* Code organization: See block comment at the top of > + aarch64-sve-builtins.def. */ > > #ifndef DEF_SME_FUNCTION_GS > #define DEF_SME_FUNCTION_GS(NAME, SHAPE, TYPES, GROUPS, PREDS) \ > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def > b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def > index 8765021d951..19249a58875 100644 > --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def > +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def > @@ -17,22 +17,8 @@ > along with GCC; see the file COPYING3. If not see > <http://www.gnu.org/licenses/>. */ > > -/* Code organisation: > - > - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get > - a little blurry. > - > - Therefore code is organised by the following rough principles: > - > - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally > - incompatible with non-streaming mode. This usually means it uses the ZA > - or ZT register. > - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a > streaming mode > - intrinsic, but either is non-streaming compatible, or theoretically > could > - be later. > - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. > - - aarch64-sve-builtins.def for common data types and group definitions > used > - across all files. */ > +/* Code organization: See block comment at the top of > + aarch64-sve-builtins.def. */ > > #define REQUIRED_EXTENSIONS sve_and_sme (AARCH64_FL_SVE2, 0) > DEF_SVE_FUNCTION (svaba, ternary_opt_n, all_integer, none) > diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def > b/gcc/config/aarch64/aarch64-sve-builtins.def > index ecd434bda35..ecd136cab08 100644 > --- a/gcc/config/aarch64/aarch64-sve-builtins.def > +++ b/gcc/config/aarch64/aarch64-sve-builtins.def > @@ -17,22 +17,22 @@ > along with GCC; see the file COPYING3. If not see > <http://www.gnu.org/licenses/>. */ > > -/* Code organisation: > - > - The lines defining if an intrinsic is for sve, sve2, sme, and sme2 can get > - a little blurry. > - > - Therefore code is organised by the following rough principles: > - > - - aarch64-sve-builtins-sme.def for any intrinsic that is fundamentally > - incompatible with non-streaming mode. This usually means it uses the ZA > - or ZT register. > - - aarch64-sve-builtins-sve2.def for any intrinsic that that is a > streaming mode > - intrinsic, but either is non-streaming compatible, or theoretically > could > - be later. > - - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2. > - - aarch64-sve-builtins.def for common data types and group definitions > used > - across all files. */ > +/* Code organization: > + > + The taxonomic lines dividing intrinsics into sve, sve2, sme, and sme2 are There is no sme2 file (neither .def or .md). > + perhaps a little non-obvious. > + > + Therefore code is organized by the following rough principles: No need for "Therefore" here, can we just say "The code is organized ..."? > + > + - aarch64-sve-builtins.def common data types, groups, and other supporting > + definitions used across all files. missing "for" > + - aarch64-sve-builtins-base.def for SVE intrinsics that are pre SVE2 and > SME. How about "for the baseline SVE intrinsics which predate SVE2 and SME."? Sorry for not suggesting this earlier. > + - aarch64-sve-builtins-sve2.def for any scalable SIMD intrinsic that is > + enabled by an SVE2+ or SME+ extension and isn't clearly streaming mode > + only. Instead of "isn't clearly streaming mode only" can we say something like "doesn't directly touch SME state (such as ZA, ZT0) and only involves regular SVE vectors and predicates" (as per Richard's commit message above). > + - aarch64-sve-builtins-sme.def for any SVE2+ or SME+ instinsic that is > + clearly streaming mode only. This usually means it uses the ZA or ZT > + registers. */ Looking at the -sme.def file, it seems that none of the intrinsics are actually enabled by an SVE2 extension (only SME), so can we drop the bit about SVE2? For the second sentence, how about: "This usually means it uses the ZA or ZT0 registers, or other SME state." Similar comments apply to the md file, of course. > > #ifndef DEF_SVE_MODE > #define DEF_SVE_MODE(A, B, C, D) > diff --git a/gcc/config/aarch64/aarch64-sve.md > b/gcc/config/aarch64/aarch64-sve.md > index b77a04cd2d2..846ed5c65d2 100644 > --- a/gcc/config/aarch64/aarch64-sve.md > +++ b/gcc/config/aarch64/aarch64-sve.md > @@ -18,23 +18,7 @@ > ;; along with GCC; see the file COPYING3. If not see > ;; <http://www.gnu.org/licenses/>. > > -;; Code organisation: > -; > -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are > -;; a little blurry. > -;; > -;; Therefore code is organised by the following rough principles: > -;; > -;; - aarch64.md: For shared parts of the architecture (such as defining > -;; registers and constants) and for instructions that operate on non-SIMD > -;; registers. > -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD > -;; registers. > -;; - aarch64-sve.md for SVE instructions that are pre SVE2. > -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible > with > -;; non-streaming mode. This usually means it uses the ZA or ZT register. > -;; - aarch64-sve2.md for any scalable SIMD instruction that either is > -;; streaming compatible, or theoretically could be later. > +;; Code organization: See block comment at the top of aarch64.md. > > ;; The file is organised into the following sections (search for the full > ;; line): > diff --git a/gcc/config/aarch64/aarch64-sve2.md > b/gcc/config/aarch64/aarch64-sve2.md > index f959837eca0..1278b9081cd 100644 > --- a/gcc/config/aarch64/aarch64-sve2.md > +++ b/gcc/config/aarch64/aarch64-sve2.md > @@ -17,24 +17,8 @@ > ;; You should have received a copy of the GNU General Public License > ;; along with GCC; see the file COPYING3. If not see > ;; <http://www.gnu.org/licenses/>. > -; > -;; Code organisation: > -; > -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are > -;; a little blurry. > -;; > -;; Therefore code is organised by the following rough principles: > -;; > -;; - aarch64.md: For shared parts of the architecture (such as defining > -;; registers and constants) and for instructions that operate on non-SIMD > -;; registers. > -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD > -;; registers. > -;; - aarch64-sve.md for SVE instructions that are pre SVE2. > -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible > with > -;; non-streaming mode. This usually means it uses the ZA or ZT register. > -;; - aarch64-sve2.md for any scalable SIMD instruction that either is > -;; streaming compatible, or theoretically could be later. > + > +;; Code organization: See block comment at the top of aarch64.md. > > ;; The file is organised into the following sections (search for the full > ;; line): > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 58e57fd65a7..ccfba7eb104 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -18,23 +18,24 @@ > ;; along with GCC; see the file COPYING3. If not see > ;; <http://www.gnu.org/licenses/>. > > -;; Code organisation: > +;; Code organization: > ; > -;; The lines of is an instruction is aarch64, simd, sve, sve2, or sme are > -;; a little blurry. > +;; The taxonomic lines dividing instructions into aarch64, simd, sve, sve2, > +;; and sme are perhaps a little non-obvious. > ;; > -;; Therefore code is organised by the following rough principles: > +;; Therefore code is organized by the following rough principles: > ;; > ;; - aarch64.md: For shared parts of the architecture (such as defining > -;; registers and constants) and for instructions that operate on non-SIMD > +;; registers and constants) and for instructions that operate on > +;; general-purpose registers. > +;; - aarch64-simd.md: For instructions that operate on Advanced SIMD > ;; registers. > -;; - aarch64-simd.md: For instructions that operate on non-scaling SIMD > -;; registers. > -;; - aarch64-sve.md for SVE instructions that are pre SVE2. > -;; - aarch64-sme.md for any scalable SIMD instruction that is incompatible > with > -;; non-streaming mode. This usually means it uses the ZA or ZT register. > -;; - aarch64-sve2.md for any scalable SIMD instruction that either is > -;; streaming compatible, or theoretically could be later. > +;; - aarch64-sve.md for SVE instructions that are pre SVE2 and SME. > +;; - aarch64-sve2.md for any scalable SIMD instruction that is enabled by an > +;; SVE2+ or SME+ extension and is not clearly non-streaming incompatible. > +;; - aarch64-sme.md for any scalable SIMD instruction that is clearly > +;; incompatible with non-streaming mode. This usually means it uses the > ZA > +;; or ZT register. Please mirror the comments from the .def file changes here, where applicable. Thanks for your patience, I think this is really getting there now, and we're moving towards a much clearer description of the division between the various files. Thanks, Alex > > ;; Register numbers > (define_constants > -- > 2.34.1 >
