From: Andrei Nichita Tirziu <[email protected]>
The optabs introduced for the new MATCH Pattern need an implementation
in the backend so that the vectorizer can complete the transformation.
The non-conditional optab is expanded to its conditional counterpart,
using an all-true predicate as a mask.
The conditional optab emits an SVE `match` or `nmatch` instructions.
The SVE backend doesn't make use of the `len` or `bias` arguments that
the conditional-len optab has, so there is no need to implement
such a version.
gcc/ChangeLog:
* config/aarch64/aarch64-sve2.md: New patterns for match,
nmatch optabs.
* config/aarch64/iterators.md: New iterator for MATCH,
NMATCH modes.
Change-Id: I1e343a332752ae34863d7b5b760176dc0eb81104
---
gcc/config/aarch64/aarch64-sve2.md | 37 ++++++++++++++++++++++++++++++
gcc/config/aarch64/iterators.md | 3 +++
2 files changed, 40 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-sve2.md
b/gcc/config/aarch64/aarch64-sve2.md
index 1aa885abedd5..28f0df901708 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -4328,6 +4328,43 @@
;; - NMATCH
;; -------------------------------------------------------------------------
+;; SVE MATCH and NMATCH instructions. These are used by the optabs
+;; `vec_match_eq_optab` and `vec_match_ne_optab`.
+;;
+;; The initial operands are (result, variants_vector, invariants_vector).
+;; A full-true mask is generated to transform it into a valid instruction.
+(define_expand "@vec_<sve_int_op>_<vpred><mode>"
+ [(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
+ (unspec:<VPRED>
+ [(match_operand:SVE_MATCH_AND_NMATCH 1 "register_operand" "w")
+ (match_operand:SVE_MATCH_AND_NMATCH 2 "register_operand" "w")]
+ SVE2_MATCH))]
+ "TARGET_SVE2 && TARGET_NON_STREAMING"
+ {
+ rtx true_pred = aarch64_ptrue_reg (<VPRED>mode);
+ emit_insn (gen_vec_<sve_int_op>_cond_<vpred><mode>
+ (operands[0], operands[1], operands[2], true_pred, operands[1]));
+ DONE;
+ }
+)
+
+;; SVE MATCH and NMATCH instructions. These are used by the optabs
+;; `cond_vec_match_eq_optab` and `cond_vec_match_ne_optab`.
+;;
+;; The operands are
+;; (result, variants_vector, invariants_vector, mask, ignored_vector).
+(define_insn "@vec_<sve_int_op>_cond_<vpred><mode>"
+ [(set (match_operand:<VPRED> 0 "register_operand" "=Upa")
+ (unspec:<VPRED>
+ [(match_operand:SVE_MATCH_AND_NMATCH 1 "register_operand" "w")
+ (match_operand:SVE_MATCH_AND_NMATCH 2 "register_operand" "w")
+ (match_operand:<VPRED> 3 "register_operand" "Upa")
+ (match_operand:SVE_MATCH_AND_NMATCH 4 "register_operand" "w")]
+ SVE2_MATCH))]
+ "TARGET_SVE2 && TARGET_NON_STREAMING"
+ "<sve_int_op>\t%0.<Vetype>, %3/z, %1.<Vetype>, %2.<Vetype>"
+)
+
;; Predicated string matching.
(define_insn "@aarch64_pred_<sve_int_op><mode>"
[(set (match_operand:<VPRED> 0 "register_operand")
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 588c89c8a176..2aee8ca5754f 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -715,6 +715,9 @@
;; Used for narrowing SVE floating point operations.
(define_mode_iterator VNx16F_NARROW [SVE_FULL_HFx2 VNx16SF])
+;; SVE modes supported by MATCH and NMATCH instructions.
+(define_mode_iterator SVE_MATCH_AND_NMATCH [VNx16QI VNx8HI])
+
;; All SVE predicate modes.
(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
--
2.52.0
