When Ram from my LLVM team was updating LLVM to enable all of Ascalon's supported extensions, he noticed my last patch missed the zvfbfmin extension.
The following was regtested on riscv64-linux with no regressions. Given this affects only Ascalon, it should be VERY low risk, so I plan on pushing this as obvious unless I hear any objections by tomorrow. Peter The previous update to Ascalon's extension list missed zvfbfmin. Add it. 2026-01-21 Peter Bergner <[email protected]> gcc/ PR target/123492 * config/riscv/riscv-cores.def (RISCV_CORE): Add zvfbfmin to tt-ascalon-d8. Signed-off-by: Peter Bergner <[email protected]> --- gcc/config/riscv/riscv-cores.def | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 6c7b87b5c6b..79a460f8176 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -148,8 +148,8 @@ RISCV_CORE("xt-c920v2", "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_" "xtheadsync", "xt-c920v2") -RISCV_CORE("tt-ascalon-d8", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfwma_zvfh_" - "zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" +RISCV_CORE("tt-ascalon-d8", "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_" + "zvfh_zvkng_zvl256b_smaia_smmpm_smnpm_smrnmi_" "smstateen_ssaia_ssstrict_svadu", "tt-ascalon-d8") -- 2.34.1
