In the function loongarch_expand_vector_init_same, if same is MEM and
the mode of same does not match imode, it will cause an ICE
in force_reg (imode, same).
PR target/123807
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_expand_vector_init_same): When same is MEM and
GET_MODE(same) != imode, first load the data from memory
and then process it further.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/pr123807.c: New test.
---
gcc/config/loongarch/loongarch.cc | 11 ++++++++++-
.../gcc.target/loongarch/vector/lsx/pr123807.c | 10 ++++++++++
2 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/pr123807.c
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 30f8bc05747..27e0c79d29a 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10436,7 +10436,16 @@ loongarch_expand_vector_init_same (rtx target, rtx
vals, unsigned nvar)
}
}
- temp = force_reg (imode, same);
+ if (GET_CODE (same) == MEM && GET_MODE (same) != imode)
+ {
+ rtx reg_tmp = gen_reg_rtx (GET_MODE (same));
+ loongarch_emit_move (reg_tmp, same);
+ temp = lowpart_subreg (imode, reg_tmp, GET_MODE (reg_tmp));
+ }
+ else
+ temp = same;
+
+ temp = force_reg (imode, temp);
switch (vmode)
{
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/pr123807.c
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/pr123807.c
new file mode 100644
index 00000000000..7ec514ae41a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/pr123807.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msimd=lsx" } */
+
+typedef long long v2i64 __attribute__ ((__vector_size__ (16)));
+v2i64 a, b;
+void
+test (int imm8)
+{
+ b = a << imm8;
+}
--
2.34.1
