On Tue, Feb 10, 2026 at 03:42:30PM +0530, Surya Kumari Jangala wrote: > Hi Mike, > > This is a very big patch, can you please break it up? > We can perhaps have one patch which have the mma.md changes, another patch > that > will contain the OPTION_MASK_DENSE_MATH changes etc etc. > More comments are inlined:
While I have re-formulated the patch, and I will be re-submitting it in a bit, ultimately when you add a new register and/or new sizes for the register, there are a lot of interlocking parts that all must be done at the same time, or else the internal consistency checks fail. The new patches are currently 5 patches: 1: Add wD constraint (like the current patch, but removing all of the mma.md insns that were switched to use wD. Currently at 141 lines. 2: Add the -mdense-math switch, but don't do anything with it. Currently 105 lines. 3: Add the support for 512-bit dense math registers (but not enable it in mma.md). As I said, you really need all of the parts to add a new register class in order for the consistency checks not to fail. At present, it is 773 lines. 4: Switch to using wD and accumulator registers in mma.md. A lot of the changes are similar (i.e. for each insn, change the d constraint to wD, changing fpr_reg_operand predicate to accumulator_operand. This is an all or nothing patch, as things will not work if you only do 1/2 of the insns at a time (since some insns would expect dense math registers and the others would expect fprs). This patch is currently at 543 lines. 5: Patch to add support for 1,024 bit dense math registers. Except for some minor changes, it is essentially the same as the current 4th patch that does this. Like in patch #3, I don't see any realistic way to split this up. It is currently 730 lines. -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
