Hi! gas expects the second operand if in memory WORD PTR rather than XMMWORD PTR. The following patch fixes it by using %w1 instead of %1, if the operand is a register, it is printed as xmm1 in both cases.
Bootstrapped/regtested on x86_64-linux and i686-linux, approved by Uros in the PR, committed to trunk. 2026-03-04 Jakub Jelinek <[email protected]> PR target/124349 * config/i386/sse.md (avx10_2_comisbf16_v8bf): Use %w1 instead of %1 for -masm=intel. * gcc.target/i386/avx10_2-pr124349.c: New test. --- gcc/config/i386/sse.md.jj 2026-03-03 12:21:14.200132286 +0100 +++ gcc/config/i386/sse.md 2026-03-03 18:12:51.943682553 +0100 @@ -5241,7 +5241,7 @@ (define_insn "avx10_2_comisbf16_v8bf" (match_operand:V8BF 1 "nonimmediate_operand" "vm") (parallel [(const_int 0)]))))] "TARGET_AVX10_2" - "vcomisbf16\t{%1, %0|%0, %1}" + "vcomisbf16\t{%1, %0|%0, %w1}" [(set_attr "prefix" "evex") (set_attr "type" "ssecomi")]) --- gcc/testsuite/gcc.target/i386/avx10_2-pr124349.c.jj 2026-03-03 18:18:42.739901491 +0100 +++ gcc/testsuite/gcc.target/i386/avx10_2-pr124349.c 2026-03-03 18:16:58.714616245 +0100 @@ -0,0 +1,17 @@ +/* PR target/124349 */ +/* { dg-do assemble { target { avx10_2 && masm_intel } } } */ +/* { dg-options "-O2 -mavx10.2 -masm=intel" } */ + +#include <x86intrin.h> + +int +foo (__m128bh v, __m128bh *p) +{ + return _mm_comilt_sbh (*p, v); +} + +int +bar (__m128bh v, __m128bh w) +{ + return _mm_comilt_sbh (w, v); +} Jakub
