Hi! These two insns were using the same operand order for both -masm=att and -masm=intel, which is ok if using the same operand for both, but not when they are different.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, approved by Uros in the PR, committed to trunk. 2026-03-05 Jakub Jelinek <[email protected]> PR target/124366 * config/i386/i386.md (@wrss<mode>, @wruss<mode>): Swap operand order for -masm=intel. * gcc.target/i386/cet-pr124366.c: New test. --- gcc/config/i386/i386.md.jj 2026-03-03 15:47:04.230275241 +0100 +++ gcc/config/i386/i386.md 2026-03-04 21:52:33.409720768 +0100 @@ -30267,7 +30267,7 @@ (define_insn "@wrss<mode>" (match_operand:SWI48 1 "memory_operand" "m")] UNSPECV_WRSS)] "TARGET_SHSTK" - "wrss<mskmodesuffix>\t%0, %1" + "wrss<mskmodesuffix>\t{%0, %1|%1, %0}" [(set_attr "length" "3") (set_attr "type" "other")]) @@ -30276,7 +30276,7 @@ (define_insn "@wruss<mode>" (match_operand:SWI48 1 "memory_operand" "m")] UNSPECV_WRUSS)] "TARGET_SHSTK" - "wruss<mskmodesuffix>\t%0, %1" + "wruss<mskmodesuffix>\t{%0, %1|%1, %0}" [(set_attr "length" "4") (set_attr "type" "other")]) --- gcc/testsuite/gcc.target/i386/cet-pr124366.c.jj 2026-03-04 21:59:21.908859607 +0100 +++ gcc/testsuite/gcc.target/i386/cet-pr124366.c 2026-03-04 22:00:36.767602436 +0100 @@ -0,0 +1,31 @@ +/* PR target/124366 */ +/* { dg-do assemble { target { cet && masm_intel } } } */ +/* { dg-options "-O2 -mshstk -masm=intel" } */ + +#include <x86intrin.h> + +void +wrssd (unsigned int x, void *y) +{ + _wrssd (x, y); +} + +void +wrussd (unsigned int x, void *y) +{ + _wrussd (x, y); +} + +#ifdef __x86_64__ +void +wrssq (unsigned long long x, void *y) +{ + _wrssq (x, y); +} + +void +wrussq (unsigned long long x, void *y) +{ + _wrussq (x, y); +} +#endif Jakub
