Enable the following macro-fusion pairs for xt-c9501fdvt:
RISCV_FUSE_LUI_ADDI
RISCV_FUSE_AUIPC_ADDI
RISCV_FUSE_SUB_SEQZ
RISCV_FUSE_ADD_ANDI
RISCV_FUSE_ADD_LD
RISCV_FUSE_ADD_ST
RISCV_FUSE_ANDI_ADD
RISCV_FUSE_LOGIC_LOGIC
RISCV_FUSE_SLLI_SRLI
RISCV_FUSE_SRLI_ADD
RISCV_FUSE_PREINDEX_LD
RISCV_FUSE_PREINDEX_ST
RISCV_FUSE_POSTINDEX_LD
RISCV_FUSE_POSTINDEX_ST
RISCV_FUSE_LDST_PAIR_INC
RISCV_FUSE_LDST_PAIR_DEC
Leave RISCV_FUSE_FLDFST_PAIR_INC and RISCV_FUSE_FLDFST_PAIR_DEC
disabled for xt-c9501fdvt; they will be enabled for future CPUs.
gcc/ChangeLog:
* config/riscv/riscv.cc (xt_c9501_tune_info): Enable supported
fusion pairs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/fusion-add-addi-andi.c: Remove the fusion xfail.
* gcc.target/riscv/fusion-add-ldst.c: Likewise.
* gcc.target/riscv/fusion-addw-adduw-ldst.c: Likewise.
* gcc.target/riscv/fusion-andi-add-addi.c: Likewise.
* gcc.target/riscv/fusion-andi-adduw-rtl.c: Likewise.
* gcc.target/riscv/fusion-arith-rtl-shapes.c: Likewise.
* gcc.target/riscv/fusion-c950-lui-auipc.c: Likewise.
* gcc.target/riscv/fusion-fp-zero-rtl.c: Likewise.
* gcc.target/riscv/fusion-ldst-pair-dec.c: Likewise.
* gcc.target/riscv/fusion-ldst-pair-inc.c: Likewise.
* gcc.target/riscv/fusion-ldst-pair-store-base.c: Likewise.
* gcc.target/riscv/fusion-load-store-type-rtl.c: Likewise.
* gcc.target/riscv/fusion-logic-logic-direction-rtl.c: Likewise.
* gcc.target/riscv/fusion-logic-logic-zbkb.c: Likewise.
* gcc.target/riscv/fusion-logic-logic.c: Likewise.
* gcc.target/riscv/fusion-memory-rtl-shapes.c: Likewise.
* gcc.target/riscv/fusion-memory-subreg-address-rtl.c: Likewise.
* gcc.target/riscv/fusion-mv-li-andi-rtl.c: Likewise.
* gcc.target/riscv/fusion-mv-self-rtl.c: Likewise.
* gcc.target/riscv/fusion-postindex-ldst.c: Likewise.
* gcc.target/riscv/fusion-postindex-unsigned-load-rtl.c: Likewise.
* gcc.target/riscv/fusion-preindex-ldst.c: Likewise.
* gcc.target/riscv/fusion-rv32-fp-losum-rtl.c: Likewise.
* gcc.target/riscv/fusion-rv32-subreg-positive-rtl.c: Likewise.
* gcc.target/riscv/fusion-slli-srli.c: Likewise.
* gcc.target/riscv/fusion-special-positive-rtl.c: Likewise.
* gcc.target/riscv/fusion-srli-add.c: Likewise.
* gcc.target/riscv/fusion-sub-seqz-snez.c: Likewise.
* gcc.target/riscv/fusion-subreg-address-rtl.c: Likewise.
* gcc.target/riscv/fusion-word-positive-rtl.c: Likewise.
---
gcc/config/riscv/riscv.cc | 11 ++++++++++-
.../gcc.target/riscv/fusion-add-addi-andi.c | 3 +--
gcc/testsuite/gcc.target/riscv/fusion-add-ldst.c | 5 ++---
.../gcc.target/riscv/fusion-addw-adduw-ldst.c | 4 ++--
.../gcc.target/riscv/fusion-andi-add-addi.c | 3 +--
.../gcc.target/riscv/fusion-andi-adduw-rtl.c | 3 +--
.../gcc.target/riscv/fusion-arith-rtl-shapes.c | 13 ++++++-------
.../gcc.target/riscv/fusion-c950-lui-auipc.c | 5 ++---
.../gcc.target/riscv/fusion-fp-zero-rtl.c | 5 ++---
.../gcc.target/riscv/fusion-ldst-pair-dec.c | 3 +--
.../gcc.target/riscv/fusion-ldst-pair-inc.c | 3 +--
.../riscv/fusion-ldst-pair-store-base.c | 5 ++---
.../gcc.target/riscv/fusion-load-store-type-rtl.c | 7 +++----
.../riscv/fusion-logic-logic-direction-rtl.c | 3 +--
.../gcc.target/riscv/fusion-logic-logic-zbkb.c | 3 +--
.../gcc.target/riscv/fusion-logic-logic.c | 3 +--
.../gcc.target/riscv/fusion-memory-rtl-shapes.c | 15 +++++++--------
.../riscv/fusion-memory-subreg-address-rtl.c | 7 +++----
.../gcc.target/riscv/fusion-mv-li-andi-rtl.c | 3 +--
.../gcc.target/riscv/fusion-mv-self-rtl.c | 6 +++---
.../gcc.target/riscv/fusion-postindex-ldst.c | 5 ++---
.../riscv/fusion-postindex-unsigned-load-rtl.c | 3 +--
.../gcc.target/riscv/fusion-preindex-ldst.c | 5 ++---
.../gcc.target/riscv/fusion-rv32-fp-losum-rtl.c | 4 ++--
.../riscv/fusion-rv32-subreg-positive-rtl.c | 12 ++++++------
gcc/testsuite/gcc.target/riscv/fusion-slli-srli.c | 3 +--
.../riscv/fusion-special-positive-rtl.c | 13 ++++++-------
gcc/testsuite/gcc.target/riscv/fusion-srli-add.c | 3 +--
.../gcc.target/riscv/fusion-sub-seqz-snez.c | 3 +--
.../gcc.target/riscv/fusion-subreg-address-rtl.c | 3 +--
.../gcc.target/riscv/fusion-word-positive-rtl.c | 5 ++---
31 files changed, 76 insertions(+), 93 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8f18a60b7c7..1a41ca5be92 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -730,7 +730,16 @@ static const struct riscv_tune_param xt_c9501_tune_info = {
false, /* overlap_op_by_pieces */
true, /* use_zero_stride_load
*/
false, /* speculative_sched_vsetvl */
- RISCV_FUSE_NOTHING, /* fusible_ops */
+ RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI
+ | RISCV_FUSE_SUB_SEQZ
+ | RISCV_FUSE_ADD_ANDI
+ | RISCV_FUSE_ADD_LD | RISCV_FUSE_ADD_ST
+ | RISCV_FUSE_ANDI_ADD | RISCV_FUSE_LOGIC_LOGIC
+ | RISCV_FUSE_SLLI_SRLI | RISCV_FUSE_SRLI_ADD
+ | RISCV_FUSE_PREINDEX_LD | RISCV_FUSE_PREINDEX_ST
+ | RISCV_FUSE_POSTINDEX_LD | RISCV_FUSE_POSTINDEX_ST
+ | RISCV_FUSE_LDST_PAIR_INC
+ | RISCV_FUSE_LDST_PAIR_DEC, /* fusible_ops */
&xt_c9501_vector_cost, /* vector cost */
"32", /* function_align */
"8", /* jump_align */
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-add-addi-andi.c
b/gcc/testsuite/gcc.target/riscv/fusion-add-addi-andi.c
index 983d40c8f6b..694794523ac 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-add-addi-andi.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-add-addi-andi.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zba -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 5 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 5 "sched2" } } */
typedef long int64_t;
typedef unsigned long uint64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-add-ldst.c
b/gcc/testsuite/gcc.target/riscv/fusion-add-ldst.c
index bc00fc2f960..7d2cf3fd2b0 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-add-ldst.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-add-ldst.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64g -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 7 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 4 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 7 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 4 "sched2" } } */
typedef signed char int8_t;
typedef unsigned char uint8_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-addw-adduw-ldst.c
b/gcc/testsuite/gcc.target/riscv/fusion-addw-adduw-ldst.c
index 4947dd9101d..0a886ec9600 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-addw-adduw-ldst.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-addw-adduw-ldst.c
@@ -1,8 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zba -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 2 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 2 "sched2" } } */
/* addw + ld should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-andi-add-addi.c
b/gcc/testsuite/gcc.target/riscv/fusion-andi-add-addi.c
index 746f865535d..871c39d2110 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-andi-add-addi.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-andi-add-addi.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zba -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 4 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 4 "sched2" } } */
typedef long int64_t;
typedef int int32_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-andi-adduw-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-andi-adduw-rtl.c
index aa87846dd99..4a92ca8e922 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-andi-adduw-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-andi-adduw-rtl.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zba -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 1 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 1 "sched2" } } */
/* andi feeding add.uw's zero-extended operand should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-arith-rtl-shapes.c
b/gcc/testsuite/gcc.target/riscv/fusion-arith-rtl-shapes.c
index 522b5a1f6fb..6d7d97c7293 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-arith-rtl-shapes.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-arith-rtl-shapes.c
@@ -1,13 +1,12 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2 -mtune=xt-c9501fdvt
-fdump-rtl-sched2" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 3 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 3 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 6 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 2 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 3 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 3 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 6 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 2 "sched2" } } */
/* subw expressed via subreg, followed by snez, should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-c950-lui-auipc.c
b/gcc/testsuite/gcc.target/riscv/fusion-c950-lui-auipc.c
index fa39ac8338e..5136266ca79 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-c950-lui-auipc.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-c950-lui-auipc.c
@@ -2,9 +2,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -O2 -mcmodel=medany
-mtune=xt-c9501fdvt -mexplicit-relocs -fno-section-anchors -fdump-rtl-sched1" }
*/
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LUI_ADDI" 1 "sched1" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_AUIPC_ADDI" 1 "sched1" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LUI_ADDI" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_AUIPC_ADDI" 1 "sched1" } } */
extern int c950_array[];
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-fp-zero-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-fp-zero-rtl.c
index 03b97a8bd25..e5aabb95299 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-fp-zero-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-fp-zero-rtl.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" } } */
/* Pre-index load into FP register ft0 should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-dec.c
b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-dec.c
index 9fe4a3eae64..29d2baf0524 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-dec.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-dec.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 4 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 4 "sched2" } }
*/
typedef int int32_t;
typedef long int64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-inc.c
b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-inc.c
index 5a14a4d8a6a..fe2ec72b5a6 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-inc.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-inc.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 4 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 4 "sched2" } }
*/
typedef int int32_t;
typedef long int64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-store-base.c
b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-store-base.c
index f09a0d4ce2f..3d4b3b9d206 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-store-base.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-ldst-pair-store-base.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 2 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 2 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 2 "sched2" } }
*/
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 2 "sched2" } }
*/
typedef long int64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-load-store-type-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-load-store-type-rtl.c
index e7f69697ee4..26708306c51 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-load-store-type-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-load-store-type-rtl.c
@@ -1,10 +1,9 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched2" } }
*/
/* An add feeding an SFmode load into a GPR should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-direction-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-direction-rtl.c
index 393dc68fe8a..b2474e6d649 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-direction-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-direction-rtl.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 2 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 2 "sched2" } } */
/* reg-operand logic followed by imm-operand logic should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-zbkb.c
b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-zbkb.c
index e485ed65184..147c4e1c9ef 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-zbkb.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic-zbkb.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zbkb -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 3 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 3 "sched2" } } */
typedef long int64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic.c
b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic.c
index 2aa8214b570..3e8335c996b 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-logic-logic.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-logic-logic.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 36 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 36 "sched2" } } */
typedef long int64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-memory-rtl-shapes.c
b/gcc/testsuite/gcc.target/riscv/fusion-memory-rtl-shapes.c
index a96851975e3..f8845515246 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-memory-rtl-shapes.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-memory-rtl-shapes.c
@@ -1,14 +1,13 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zfh -mabi=lp64d -mexplicit-relocs -O2
-mtune=xt-c9501fdvt -fdump-rtl-sched2" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 3 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 1 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 3 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 2 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 3 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 3 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 2 "sched2" } }
*/
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_DEC" 1 "sched2" } }
*/
extern long fusion_memory_symbol;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-memory-subreg-address-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-memory-subreg-address-rtl.c
index 208f63f6553..4b26b384883 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-memory-subreg-address-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-memory-subreg-address-rtl.c
@@ -1,10 +1,9 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -O2 -fschedule-insns
-mtune=xt-c9501fdvt -fdump-rtl-sched1" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched1" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 1 "sched1" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 1 "sched1" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 1 "sched1" } } */
/* add followed by a load addressed through a subreg should fuse. */
long __RTL (startwith ("sched1"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-mv-li-andi-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-mv-li-andi-rtl.c
index ce8d2de28c3..d26cbb220fc 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-mv-li-andi-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-mv-li-andi-rtl.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 2 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 2 "sched2" } } */
/* mv followed by andi should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-mv-self-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-mv-self-rtl.c
index 8850c694ba6..aff74505afd 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-mv-self-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-mv-self-rtl.c
@@ -1,9 +1,9 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -O2 -fno-dce -mtune=xt-c9501fdvt
-fdump-rtl-sched2-details" } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" } } */
/* andi followed by a self-move should still fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-postindex-ldst.c
b/gcc/testsuite/gcc.target/riscv/fusion-postindex-ldst.c
index 932a21cacea..3b7586b66d3 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-postindex-ldst.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-postindex-ldst.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-funroll-loops"
"-flto" } } */
/* { dg-options "-march=rv64gc_zfh -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 7 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 7 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 7 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 7 "sched2" } } */
typedef signed char int8_t;
typedef short int16_t;
diff --git
a/gcc/testsuite/gcc.target/riscv/fusion-postindex-unsigned-load-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-postindex-unsigned-load-rtl.c
index b516e865dc6..f2365ed003b 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-postindex-unsigned-load-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-postindex-unsigned-load-rtl.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_LD" 1 "sched2" } } */
/* Unsigned byte load followed by a post-index update should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-preindex-ldst.c
b/gcc/testsuite/gcc.target/riscv/fusion-preindex-ldst.c
index 607e7610fc1..9c3fa06c9d6 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-preindex-ldst.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-preindex-ldst.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-funroll-loops"
"-flto" } } */
/* { dg-options "-march=rv64gc_zfh -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 6 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 6 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 6 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_ST" 6 "sched2" } } */
typedef signed char int8_t;
typedef short int16_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-rv32-fp-losum-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-rv32-fp-losum-rtl.c
index 4a94a6e5a02..5050f36d333 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-rv32-fp-losum-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-rv32-fp-losum-rtl.c
@@ -1,8 +1,8 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv32gc -mabi=ilp32d -mexplicit-relocs -O2 -fno-dce
-mstrict-align -mtune=xt-c9501fdvt -fdump-rtl-sched2-details" } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched2" } } */
extern double fusion_rv32_fp_symbol;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-rv32-subreg-positive-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-rv32-subreg-positive-rtl.c
index 59a84d196ae..51894e29f59 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-rv32-subreg-positive-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-rv32-subreg-positive-rtl.c
@@ -1,12 +1,12 @@
/* { dg-do compile { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv32gc -mabi=ilp32d -O2 -fno-dce -fschedule-insns
-mtune=xt-c9501fdvt -fdump-rtl-sched1-details" } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched1" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched1" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 1 "sched1" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched1" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched1" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched1" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_LD" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ST" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_PREINDEX_LD" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_POSTINDEX_ST" 1 "sched1" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched1" } }
*/
/* On RV32, an add feeding a load via the low subreg half should fuse. */
int __RTL (startwith ("sched1"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-slli-srli.c
b/gcc/testsuite/gcc.target/riscv/fusion-slli-srli.c
index 4bf56e5e876..c460436cb28 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-slli-srli.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-slli-srli.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 4 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 4 "sched2" } } */
typedef unsigned long uint64_t;
typedef unsigned int uint32_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-special-positive-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-special-positive-rtl.c
index 94277c8cb3a..a6a01faa1aa 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-special-positive-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-special-positive-rtl.c
@@ -1,13 +1,12 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 1 "sched2" {
xfail *-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 1 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 1 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ADD_ANDI" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_ANDI_ADD" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LOGIC_LOGIC" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 1 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 1 "sched2" } } */
extern long fusion_low_symbol;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-srli-add.c
b/gcc/testsuite/gcc.target/riscv/fusion-srli-add.c
index 0fe58cbb785..9bd192b1f2a 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-srli-add.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-srli-add.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc_zba -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 3 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 3 "sched2" } } */
typedef long int64_t;
typedef unsigned long uint64_t;
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-sub-seqz-snez.c
b/gcc/testsuite/gcc.target/riscv/fusion-sub-seqz-snez.c
index 20c841c9019..f2cb635197d 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-sub-seqz-snez.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-sub-seqz-snez.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 2 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SUB_SEQZ" 2 "sched2" } } */
/* sub + seqz should fuse. */
long __RTL (startwith ("sched2"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-subreg-address-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-subreg-address-rtl.c
index ccff256f5e0..011c3c030a3 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-subreg-address-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-subreg-address-rtl.c
@@ -1,8 +1,7 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fschedule-insns -fdump-rtl-sched1-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched1" {
xfail *-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_LDST_PAIR_INC" 1 "sched1" } }
*/
/* A load pair addressed through a subreg of a wider register should fuse. */
long __RTL (startwith ("sched1"))
diff --git a/gcc/testsuite/gcc.target/riscv/fusion-word-positive-rtl.c
b/gcc/testsuite/gcc.target/riscv/fusion-word-positive-rtl.c
index 665c8e909dc..f53a658f7b2 100644
--- a/gcc/testsuite/gcc.target/riscv/fusion-word-positive-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/fusion-word-positive-rtl.c
@@ -1,9 +1,8 @@
/* { dg-do compile { target { rv64 } } } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-O[sgz]" "-flto" } } */
/* { dg-options "-march=rv64gc -mabi=lp64d -mtune=xt-c9501fdvt -O2
-fdump-rtl-sched2-details" } */
-/* No tune enables these fusion pairs yet. */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 2 "sched2" { xfail
*-*-* } } } */
-/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 2 "sched2" { xfail
*-*-* } } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SRLI_ADD" 2 "sched2" } } */
+/* { dg-final { scan-rtl-dump-times "RISCV_FUSE_SLLI_SRLI" 2 "sched2" } } */
/* Raw SImode slli followed by raw SImode srli should fuse. */
int __RTL (startwith ("sched2"))
--
2.52.0
