On Mon, Dec 10, 2012 at 12:31 PM, Andreas Krebbel <kreb...@linux.vnet.ibm.com> wrote: > Hi, > > building an SPU compiler on a 64 bit host system currently fails with: > > spu.md:4394: error: cast from ‘rtx_def**’ to ‘int’ loses precision > > In the SPU backend several patterns mention the operands array in the > insn condition in order to prevent a warning about missing modes to be > issued. Interpreting the term "operands" as condition fails when it > is evaluated on a 64 bit host. Turning it into a comparison fixes > this for me. > > Ok to apply?
Looks obvious to me. It even looks less weird this way. Thanks, Richard. > Bye, > > -Andreas- > > > 2012-12-10 Andreas Krebbel <andreas.kreb...@de.ibm.com> > > * config/spu/spu.md: Replace "operands" with "operands != NULL" in > insn conditions. > > --- > gcc/config/spu/spu.md | 16 !!!!!!!!!!!!!!!! > 1 file changed, 16 modifications(!) > > Index: gcc/config/spu/spu.md > =================================================================== > *** gcc/config/spu/spu.md.orig > --- gcc/config/spu/spu.md > *************** > *** 1066,1072 **** > [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r")] UNSPEC_CG))] > ! "operands" > "cg\t%0,%1,%2") > > (define_insn "cgx_<mode>" > --- 1066,1072 ---- > [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r")] UNSPEC_CG))] > ! "operands != NULL" > "cg\t%0,%1,%2") > > (define_insn "cgx_<mode>" > *************** > *** 1074,1080 **** > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_CGX))] > ! "operands" > "cgx\t%0,%1,%2") > > (define_insn "addx_<mode>" > --- 1074,1080 ---- > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_CGX))] > ! "operands != NULL" > "cgx\t%0,%1,%2") > > (define_insn "addx_<mode>" > *************** > *** 1082,1088 **** > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_ADDX))] > ! "operands" > "addx\t%0,%1,%2") > > > --- 1082,1088 ---- > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_ADDX))] > ! "operands != NULL" > "addx\t%0,%1,%2") > > > *************** > *** 1189,1195 **** > [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r")] UNSPEC_BG))] > ! "operands" > "bg\t%0,%2,%1") > > (define_insn "bgx_<mode>" > --- 1189,1195 ---- > [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r")] UNSPEC_BG))] > ! "operands != NULL" > "bg\t%0,%2,%1") > > (define_insn "bgx_<mode>" > *************** > *** 1197,1203 **** > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_BGX))] > ! "operands" > "bgx\t%0,%2,%1") > > (define_insn "sfx_<mode>" > --- 1197,1203 ---- > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_BGX))] > ! "operands != NULL" > "bgx\t%0,%2,%1") > > (define_insn "sfx_<mode>" > *************** > *** 1205,1211 **** > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_SFX))] > ! "operands" > "sfx\t%0,%2,%1") > > (define_insn "subti3" > --- 1205,1211 ---- > (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand 3 "spu_reg_operand" "0")] UNSPEC_SFX))] > ! "operands != NULL" > "sfx\t%0,%2,%1") > > (define_insn "subti3" > *************** selb\t%0,%4,%0,%3" > *** 4018,4024 **** > (define_insn "extend_compare<mode>" > [(set (match_operand:ALL 0 "spu_reg_operand" "=r") > (unspec:ALL [(match_operand 1 "spu_reg_operand" "r")] > UNSPEC_EXTEND_CMP))] > ! "operands" > "fsm\t%0,%1" > [(set_attr "type" "shuf")]) > > --- 4018,4024 ---- > (define_insn "extend_compare<mode>" > [(set (match_operand:ALL 0 "spu_reg_operand" "=r") > (unspec:ALL [(match_operand 1 "spu_reg_operand" "r")] > UNSPEC_EXTEND_CMP))] > ! "operands != NULL" > "fsm\t%0,%1" > [(set_attr "type" "shuf")]) > > *************** selb\t%0,%4,%0,%3" > *** 4391,4397 **** > (unspec [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand:TI 3 "spu_reg_operand" "r")] UNSPEC_SHUFB))] > ! "operands" > "shufb\t%0,%1,%2,%3" > [(set_attr "type" "shuf")]) > > --- 4391,4397 ---- > (unspec [(match_operand 1 "spu_reg_operand" "r") > (match_operand 2 "spu_reg_operand" "r") > (match_operand:TI 3 "spu_reg_operand" "r")] UNSPEC_SHUFB))] > ! "operands != NULL" > "shufb\t%0,%1,%2,%3" > [(set_attr "type" "shuf")]) > >