Hello Richard, > > cvt.w.s is replaced by trunc.w.s. This seems to work. > > Probably showing my ignorance, but I couldn't see this in the patch.
trunc.w.s is enabled by ISA_HAS_TRUNC_W_S. This automatically disables cvt.w.s, because trunc.w.s is preferred. > > I disabled 64 bit FPU instructions by "-msoft-float". This works, but > > using "-msingle-float" fails. This would be the better > > configuration. There are still 64 bit FPU instructions used (e.g. "dmfc1 > > $2,$f0" when using "long double" multiplication). So "-msingle-float" > > doesn't seem to work on generic mips64-linux-gnu. > > Right. That combination hasn't really been defined. What happens > for plain doubles? This seems to work. There are no unsupported instructions generated. > Do you pass those in FPRs or GPRs? I used -mhard-float together with -msingle-float, so it is using FPRs. > The n32 TImode support you mention uses pairs of GPRs, whereas I imagine > you'd eventually want to use a single 128-bit GPR. Is that right? Most old PS2 code will work when supporting this: typedef unsigned int __u128 __attribute__((mode(TI))); This is currently working with n32 ABI without any change, but not in o32 ABI. Support for 128-bit GPR would be better, so we have full compatibility to old PS2 code. > For the record, I think all those patches would be > too invasive this late into the 4.8 cycle so would have to wait for 4.9. OK. I also want to go step by step here. > Please use ISA_HAS_* for consistency with other macros. I think it'd > be better to drop the '(integer)'. OK. I thought ISA_HAS_* was related to MIPS ISA. My stuff is only related to one CPU here. > Several other cases later on, I won't > bore you with them all :-) I rework it and try to get it stable and tested. Best regards Jürgen