My bad for missing the patch. As stated in previous message, the patch has
already been applied to ARM-Embedded-4_7-Branch.
Thanks.
> -----Original Message-----
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-ow...@gcc.gnu.org]
On
> Behalf Of Bin Cheng
> Sent: Friday, March 01, 2013 1:18 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Joey Ye
> Subject: [PATCH ARM-Embedded-4_7-branch] fixing incoorect instruction
length
> in checkin r193980
>
> Hi,
> On ARM-Embedded-4_7 branch, check-in(r193980) causes a "branch out of
range"
> bug. Root cause is the incorrect instruction length set by that check-in.
> Since the length of instruction should strictly reflect the pattern it
matches,
> this patch fixes it by correcting the length.
>
> Patch applied to ARM-Embedded-4_7-branch as r196368.
>
> Thanks.
>
>
> 2013-03-01 Bin Cheng <bin.ch...@arm.com>
>
> * config/arm/arm.md (*arm_addsi3, *arm_subsi3_insn, *arm_mulsi3_v6)
> (*arm_andsi3_insn, andsi_notsi_si, *iorsi3_insn, *arm_xorsi3)
> (*arm_shiftsi3): Change attribute length from 2 to 4 for all
> alternatives.
>
>
>
>
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 196332)
+++ gcc/config/arm/arm.md (working copy)
@@ -746,7 +746,7 @@
operands[1], 0);
DONE;
"
- [(set_attr "length" "2,4,4,4,4,4,2,4,4,4,4,16")
+ [(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*,*,t2,t2,t2,*,*,t2,t2,*")]
)
@@ -1234,7 +1234,7 @@
INTVAL (operands[1]), operands[0], operands[2], 0);
DONE;
"
- [(set_attr "length" "4,2,4,4,16")
+ [(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "arch" "*,t2,*,*,*")]
)
@@ -1360,7 +1360,7 @@
(match_operand:SI 2 "s_register_operand" "0,r")))]
"TARGET_32BIT && arm_arch6"
"mul%?\\t%0, %1, %2"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "4,4")
(set_attr "insn" "mul")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*")]
@@ -2213,7 +2213,7 @@
INTVAL (operands[2]), operands[0], operands[1], 0);
DONE;
"
- [(set_attr "length" "2,2,4,4,16")
+ [(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,t2,*,*,*")]
)
@@ -2797,7 +2797,7 @@
(match_operand:SI 1 "s_register_operand" "0,r")))]
"TARGET_32BIT"
"bic%?\\t%0, %1, %2"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "4,4")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*")]
)
@@ -2943,7 +2943,7 @@
INTVAL (operands[2]), operands[0], operands[1], 0);
DONE;
}
- [(set_attr "length" "2,4,4,16")
+ [(set_attr "length" "4,4,4,16")
(set_attr "arch" "t2,32,t2,32")
(set_attr "predicable" "yes")])
@@ -3080,7 +3080,7 @@
INTVAL (operands[2]), operands[0], operands[1], 0);
DONE;
}
- [(set_attr "length" "2,4,16")
+ [(set_attr "length" "4,4,16")
(set_attr "predicable" "yes")
(set_attr "arch" "t2,*,*")]
)
@@ -3692,7 +3692,7 @@
(match_operand:SI 2 "reg_or_int_operand" "l,rM")]))]
"TARGET_32BIT"
"* return arm_output_shift(operands, 0);"
- [(set_attr "length" "2,4")
+ [(set_attr "length" "4,4")
(set_attr "predicable" "yes")
(set_attr "shift" "1")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
