On 12/04/13 12:38, Hurugalawadi, Naveen wrote:
Hi,
Please find attached the patch that implements addition and Subtraction
by setting flags instructions in extend and shift_extend mode for
aarch64 target.
The patch for Add/Sub instructions by setting flags in shift mode is
already posted.
Testcase have been added for these instructions.
Please review the same and let me know if there should be any
modifications in the patch.
Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). No new regressions.
Thanks,
Naveen
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+typedef long long s64;
+
+int
+subs_ext (s64 a, int b, int c)
+{
+ s64 d = a - b;
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw"
} } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_shift_ext (s64 a, int b, int c)
+{
+ s64 d = (a - ((s64)b << 3));
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw
3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
This won't test what you think it does. The first regexp will also
match on the same patterns that the second one does, since it's a
sub-expression of the latter.
If you're going to do it in one file you'll need to use
scan-assembler-times.
R.
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