On 06/06/13 14:36, Kyrylo Tkachov wrote:
Hi all,
This patch updates the fixed-point math patterns in arm-fixed.md to
conform to new IT block rules in ARMv8. The add/sub instructions can be
placed in an IT block if they use the low registers.
The other more exotic variants (ssub, uqadd etc) do not have 16-bit
encodings and can therefore not be conditionalised by the new rules.
Tested together with the other patches in the series by bootstrap on a
Cortex-A15 and regtest arm-none-eabi on qemu and model.
Ok for trunk?
Thanks,
Kyrill
2013-06-06 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm-fixed.md (add<mode>3,usadd<mode>3,ssadd<mode>3,
sub<mode>3, ussub<mode>3, sssub<mode>3, arm_ssatsihi_shift,
arm_usatsihi):
Adjust alternatives for arm_restrict_it.
(define_insn "add<mode>3"
- [(set (match_operand:FIXED 0 "s_register_operand" "=r")
- (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r")
- (match_operand:FIXED 2 "s_register_operand" "r")))]
+ [(set (match_operand:FIXED 0 "s_register_operand" "=r,l")
+ (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "r,l")
+ (match_operand:FIXED 2 "s_register_operand" "r,l")))]
It would probably be better to put the 'l' variant first. This should
encourage register allocation to prefer low registers and that might
lead to other optimizations later on. Similarly for sub<mode>3.
OK with that change.
R.
