Hi all, This patch adjusts the mov* patterns in the arm backend to generate code appropriate for -mrestrict-it. The rules are: moves between any two registers are allowed to be in IT blocks. mov immediate are allowed if the immediate is 8-wide and the register is a low register.
The splitters that generate explicit cond_exec moves are adjusted to conform
to these rules, therefore making this patch self-contained.
The "Ts" constraint is introduced which evaluates to the low regs when
arm_restrict_it is on, and to the general regs otherwise.
Bootstrapped on Cortex-A15 and tested on model and qemu on arm-none-eabi for
ARMv7 and ARMv8.
Ok for trunk?
Thanks,
Kyrill
2013-06-20 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/constraints.md (Ts): New constraint.
* config/arm/arm.md (arm_movqi_insn): Add alternatives for
16-bit encodings.
(compare_scc): Use "Ts" constraint for operand 0.
(ior_scc_scc): Likewise.
(and_scc_scc): Likewise.
(and_scc_scc_nodom): Likewise.
(ior_scc_scc_cmp): Likewise for operand 7.
(and_scc_scc_cmp): Likewise.
* config/arm/thumb2.md (thumb2_movsi_insn):
Add alternatives for 16-bit encodings.
(thumb2_movhi_insn): Likewise.
(thumb2_movsicc_insn): Likewise.
(thumb2_and_scc): Take 'and' outside cond_exec. Use "Ts" constraint.
(thumb2_negscc): Use "Ts" constraint.
Move mvn instruction outside cond_exec block.
* config/arm/vfp.md (thumb2_movsi_vfp): Add alternatives
for 16-bit encodings.
09-mov-patterns.patch
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