"Steve Ellcey " <sell...@mips.com> writes:
> While doing some size measurements and optimization I found that using the
> t0 through t7 registers on MIPS in MIPS16 mode resulted in larger code. This
> is because you cannot actually do any operations on these registers in MIPS16
> mode but can only move data to or from them.
That was always the case though. These registers weren't enabled because
you can do operations on them. They were enabled because they should make
ideal spill space. Moves to and from these registers always take 2 bytes,
whereas stack spills take either 2 or 4 bytes (as well as being slower).
So it sounds like the problem is that the heuristics aren't tuned properly.
Disabling the registers seems like papering over the problem rather than
fixing it. But since no-one is likely to do the work to fix the heuristics,
that isn't a good enough reason to reject the patch.
> + /* In MIPS16 mode using the $t registers for reload results in code
> + that is larger (and slightly faster) then if we do not use them so
> + if optimizing for size, do not use them. */
> + if (optimize_size)
> + {
> + fixed_regs[8] = call_used_regs[8] = 1;
> + fixed_regs[9] = call_used_regs[9] = 1;
> + fixed_regs[10] = call_used_regs[10] = 1;
> + fixed_regs[11] = call_used_regs[11] = 1;
> + fixed_regs[12] = call_used_regs[12] = 1;
> + fixed_regs[13] = call_used_regs[13] = 1;
> + fixed_regs[14] = call_used_regs[14] = 1;
> + fixed_regs[15] = call_used_regs[15] = 1;
> + }
Please combine this with the previous block though, since the comment here
contradicts the comment there. It would also be worth saying why you
keep $24 (for CMP and CMPI) and $25 (for SVR4 PIC).
Please also run some sanity checks for -mabi=eabi and functions that
have 5+ arguments (all used) to make sure that they still work.
Thanks,
Richard
