Hi,
We don't really need to split the types on these
instructions. The ARM backend already has suitable descriptions
of things like mla and smlal. Use them.
Regression tested on aarch64-none-elf with no regressions.
OK?
Thanks,
James
---
2013-09-06 James Greenhalgh <[email protected]>
* config/aarch64/aarch64.md
(*madd<mode>): Fix type attribute.
(*maddsi_uxtw): Likewise.
(*msub<mode>): Likewise.
(*msubsi_uxtw): Likewise.
(<su_optab>maddsidi4): Likewise.
(<su_optab>msubsidi4): Likewise.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ded37efb4c86130af8dd82db66d50cc227bfeff0..e28764da5dd608259098d3150783e6eacd09be27 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2281,7 +2281,7 @@ (define_insn "*madd<mode>"
""
"madd\\t%<w>0, %<w>1, %<w>2, %<w>3"
[(set_attr "v8type" "madd")
- (set_attr "type" "mul")
+ (set_attr "type" "mla")
(set_attr "mode" "<MODE>")]
)
@@ -2295,7 +2295,7 @@ (define_insn "*maddsi_uxtw"
""
"madd\\t%w0, %w1, %w2, %w3"
[(set_attr "v8type" "madd")
- (set_attr "type" "mul")
+ (set_attr "type" "mla")
(set_attr "mode" "SI")]
)
@@ -2308,7 +2308,7 @@ (define_insn "*msub<mode>"
""
"msub\\t%<w>0, %<w>1, %<w>2, %<w>3"
[(set_attr "v8type" "madd")
- (set_attr "type" "mul")
+ (set_attr "type" "mla")
(set_attr "mode" "<MODE>")]
)
@@ -2323,7 +2323,7 @@ (define_insn "*msubsi_uxtw"
""
"msub\\t%w0, %w1, %w2, %w3"
[(set_attr "v8type" "madd")
- (set_attr "type" "mul")
+ (set_attr "type" "mla")
(set_attr "mode" "SI")]
)
@@ -2373,7 +2373,7 @@ (define_insn "<su_optab>maddsidi4"
""
"<su>maddl\\t%0, %w1, %w2, %3"
[(set_attr "v8type" "maddl")
- (set_attr "type" "mul")
+ (set_attr "type" "<su>mlal")
(set_attr "mode" "DI")]
)
@@ -2387,7 +2387,7 @@ (define_insn "<su_optab>msubsidi4"
""
"<su>msubl\\t%0, %w1, %w2, %3"
[(set_attr "v8type" "maddl")
- (set_attr "type" "mul")
+ (set_attr "type" "<su>mlal")
(set_attr "mode" "DI")]
)
