On Fri, Sep 13, 2013 at 11:35 AM, James Greenhalgh <james.greenha...@arm.com> wrote: > > Hi, > > The vset<q>_lane_<fpsu><8,16,32,64> intrinsics are currently > written useing assembler, but can be easily expressed > in C. > > As I expect we will want to efficiently compose these intrinsics > I've added them as macros, just as was done with the vget_lane > intrinsics. > > Regression tested for aarch64-none-elf and a new testcase > added to ensure these intrinsics generate the expected > instruction. > > OK?
I don't think this works for big-endian due to the way ARM decided the lanes don't match up with array entry there. Thanks, Andrew Pinski > > Thanks, > James > > --- > gcc/ > > 2013-09-13 James Greenhalgh <james.greenha...@arm.com> > > * config/aarch64/arm_neon.h > (__aarch64_vset_lane_any): New. > (__aarch64_vset<q>_lane_<fpsu><8,16,32,64>): Likewise. > (vset<q>_lane_<fpsu><8,16,32,64>): Use new macros. > > gcc/testsuite > > 2013-09-13 James Greenhalgh <james.greenha...@arm.com> > > * gcc.target/aarch64/vect_set_lane_1.c: New.
