On Mon, Oct 21, 2013 at 5:51 PM, Michael Meissner wrote: > What I'm doing is adding secondary reload support so that up until reload > time, > we can represent VSX addresses as reg+offset, and in secondary reload, create > the addition instructions to put the offset in a base register. I haven't > made > any changes to the machine independent portions of the compiler. As long as > IRA uses the secondary reload interface, it should be ok. However, right now, > I need to focus most of my attention on getting the secondary reload support > to > work. > > One thing that I've asked for before, but to remind you, is I really, really > wish secondary reload could allocate two scratch registers if it is given an > insn that takes 4 arguments. Right now, I'm allocating a TFmode scratch, > since > that gives 2 registers, but future changes will want TFmode to go into a > single > vector register, and I will need to create another type, like V4DI that does > take 2 registers. The case that this is needed for is moving an item from > GPRs > to VSX registers that takes 2 GPR registers, such as moving 128-bit items in > 64-bit mode, or 64-bit items in 32-bit mode. I need two registers to do the > move into, and then I will do the combine operation.
Eh, perhaps I'm missing something, but... Isn't one of the great advantages of LRA over reload, that LRA allows you to create new pseudos so that you shouldn't ever need secondary reloads?? Ciao! Steven
