Hi all,This patch adds the rtx costs table for the Cortex-A53. It goes in the new aarch-cost-tables.h file because we will want to share it with AArch64.
We add a corresponding tuning struct and set the tuning from generic cortex tuning to the new one.
Tested arm-none-eabi on model. Ok for trunk? Thanks, Kyrill 2013-11-15 Kyrylo Tkachov <kyrylo.tkac...@arm.com> * config/arm/aarch-cost-tables.h (cortexa53_extra_costs): New table. * config/arm/arm.c (arm_cortex_a53_tune): New. * config/arm/arm-cores.def (cortex-a53): Use cortex_a53 tuning struct.
diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 4b36abe..d3e7dd2 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -122,5 +122,106 @@ const struct cpu_cost_table generic_extra_costs = } }; +const struct cpu_cost_table cortexa53_extra_costs = +{ + /* ALU */ + { + 0, /* Arith. */ + 0, /* Logical. */ + COSTS_N_INSNS (1), /* Shift. */ + COSTS_N_INSNS (2), /* Shift_reg. */ + COSTS_N_INSNS (1), /* Arith_shift. */ + COSTS_N_INSNS (2), /* Arith_shift_reg. */ + COSTS_N_INSNS (1), /* Log_shift. */ + COSTS_N_INSNS (2), /* Log_shift_reg. */ + 0, /* Extend. */ + COSTS_N_INSNS (1), /* Extend_arith. */ + COSTS_N_INSNS (1), /* Bfi. */ + COSTS_N_INSNS (1), /* Bfx. */ + 0, /* Clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (1), /* Simple. */ + COSTS_N_INSNS (2), /* Flag_setting. */ + COSTS_N_INSNS (1), /* Extend. */ + COSTS_N_INSNS (1), /* Add. */ + COSTS_N_INSNS (1), /* Extend_add. */ + COSTS_N_INSNS (7) /* Idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (2), /* Simple. */ + 0, /* Flag_setting (N/A). */ + COSTS_N_INSNS (2), /* Extend. */ + COSTS_N_INSNS (2), /* Add. */ + COSTS_N_INSNS (2), /* Extend_add. */ + COSTS_N_INSNS (15) /* Idiv. */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (1), /* Load. */ + COSTS_N_INSNS (1), /* Load_sign_extend. */ + COSTS_N_INSNS (1), /* Ldrd. */ + COSTS_N_INSNS (1), /* Ldm_1st. */ + 1, /* Ldm_regs_per_insn_1st. */ + 2, /* Ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* Loadf. */ + COSTS_N_INSNS (1), /* Loadd. */ + COSTS_N_INSNS (1), /* Load_unaligned. */ + 0, /* Store. */ + 0, /* Strd. */ + 0, /* Stm_1st. */ + 1, /* Stm_regs_per_insn_1st. */ + 2, /* Stm_regs_per_insn_subsequent. */ + 0, /* Storef. */ + 0, /* Stored. */ + COSTS_N_INSNS (1) /* Store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (15), /* Div. */ + COSTS_N_INSNS (3), /* Mult. */ + COSTS_N_INSNS (7), /* Mult_addsub. */ + COSTS_N_INSNS (7), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (1), /* Fpconst. */ + COSTS_N_INSNS (2), /* Neg. */ + COSTS_N_INSNS (1), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (30), /* Div. */ + COSTS_N_INSNS (3), /* Mult. */ + COSTS_N_INSNS (7), /* Mult_addsub. */ + COSTS_N_INSNS (7), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (1), /* Fpconst. */ + COSTS_N_INSNS (2), /* Neg. */ + COSTS_N_INSNS (1), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* Alu. */ + } +}; + + #endif /* GCC_AARCH_COST_TABLES_H */ diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index d664e73..119dc33 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -129,7 +129,7 @@ ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) -ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex) +ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a53) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 2f3ea72..1e12001 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1505,6 +1505,22 @@ const struct tune_params arm_cortex_a15_tune = false /* Prefer Neon for 64-bits bitops. */ }; +const struct tune_params arm_cortex_a53_tune = +{ + arm_9e_rtx_costs, + &cortexa53_extra_costs, + NULL, /* Scheduler cost adjustment. */ + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ + &arm_default_vec_cost, /* Vectorizer costs. */ + false /* Prefer Neon for 64-bits bitops. */ +}; + /* Branches can be dual-issued on Cortex-A5, so conditional execution is less appealing. Set max_insns_skipped to a low value. */