On 26/11/13 14:49, Kyrill Tkachov wrote: > Hi all, > > In the spirit of stage3, this patch fixes a regression in > gcc.target/arm/negdi-2.c when compiling for big-endian with the new rtx costs > for the Cortex-A9. We ended up generating an extra mov because combine > generates > a zero-extend operation that would later get split into two moves (versus the > old way where combine would generate two moves and reload would eliminate one > of > them). The fix is three-fold: > > - We fix the cost calculation for zero-extend when extending from SImode to > DImode by initialising the cost correctly. > - We add a splitter to match the negate-and-extend operation and break it > down > into its constituent operations early on. > - Generalise the register pattern for which we scan in the testcase itself > since > for big-endian the negated part goes into r1, not r0. > > Tested arm-none-eabi on qemu. > > Ok for trunk? > > Thanks, > Kyrill > > 2013-11-26 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/59290 > * config/arm/arm.md (*zextendsidi_negsi): New pattern. > * config/arm/arm.c (arm_new_rtx_costs): Initialise cost correctly > for zero_extend case. > > 2013-11-26 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/59290 > * gcc.target/arm/negdi-2.c: Scan more general register names. >
OK. R.
