On 30/01/14 20:47, Jakub Jelinek wrote:
On Thu, Jan 30, 2014 at 08:27:47PM +0000, Paulo Matos wrote:
Yes, it looks strange but it was the way we came up with to
implement an instruction that loads from a pair of addresses.
From what I wrote previously to Richard.
"We have an instruction that loads two 32 bit values into a lower
and upper parts of a 64bit register using a base register and a 64
bit register used as a double index.
So,
r1 <- [r0, r2]
means:
low(r1) = [r0 + low(r2)]
high(r1) = [r0 + high(r2)]"
That sounds like gather instruction e.g. i?86 AVX2/AVX512F has.
I don't like using vector mode for the address though, i?86 uses UNSPECs and
IMNSHO you should too. Or express it as vec_concat of two MEM loads
where address of each one will be the base + vec_select of the vector
register.
Jakub
I will take a closer look at our pattern and how i?86 implements it.
Thanks for the advice.
Paulo Matos
