> -----Original Message-----
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Terry Guo
> Sent: Friday, March 28, 2014 3:48 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [Patch]Simplify SUBREG with operand whose target bits are cleared
> by AND operation
>
> Hi there,
>
> When compile below case for ARM Thumb-2 target:
>
> long long int
> test (unsigned long long int a, unsigned int b)
> {
> return (a & 0xFFFFFFFF) * b;
> }
>
> I find the GCC function simplify_subreg fails to simplify rtx (subreg:SI
> (and:DI (reg/v:DI 115 [ a ]) (const_int 4294967295 [0xffffffff])) 4) to
zero
> during the fwprop1 pass, considering the fact that the high 32-bit part of
> (a & 0xFFFFFFFF) is zero. This leads to some unnecessary multiplications
for
> high 32-bit part of the result of AND operation. The attached patch is
> trying to improve simplify_rtx to handle such case. Other target like x86
> seems hasn't such issue because it generates different RTX to handle 64bit
> multiplication on a 32bit machine.
>
> Bootstrapped gcc on x86 machine, no problem. Tested with gcc regression
> test
> for x86 and Thumb2, no regression.
>
> Is it OK to stage-1?
>
> BR,
> Terry
Sorry for missing the ChangeLog part:
gcc/
2014-03-28 Terry Guo <terry....@arm.com>
* fwprop.c (simplify_subreg): Handle case that bits are
cleared by AND operation.
gcc/testsuite/
2014-03-28 Terry Guo <terry....@arm.com>
* gcc.target/arm/umull.c: New testcase.
