On 28/03/14 14:21, Ramana Radhakrishnan wrote:
On Wed, Mar 19, 2014 at 9:55 AM, Kyrill Tkachov <kyrylo.tkac...@arm.com> wrote:
Hi all,
This patch adds a recogniser for the bitmask,shift,orr sequence of
instructions that can be used to reverse the bytes in 16-bit halfwords (for
the sequence itself look at the testcase included in the patch). This can be
implemented with a rev16 instruction.
Since the shifts can occur in any order and there are no canonicalisation
rules for where they appear in the expression we have to have two patterns
to match both cases.
The rtx costs function is updated to recognise the pattern and cost it
appropriately by using the rev field of the cost tables introduced in patch
[1/3]. The rtx costs helper functions that are used to recognise those
bitwise operations are placed in config/arm/aarch-common.c so that they can
be reused by both arm and aarch64.
The ARM bits of this are OK if there are no regressions.
I've added an execute testcase but no scan-assembler tests since
conceptually in the future the combiner might decide to not use a rev
instruction due to rtx costs. We can at least test that the code generated
is functionally correct though.
Tested aarch64-none-elf.
What about arm-none-eabi :) ?
Tested arm-none-eabi and bootstrap on arm linux together with patch [3/3] in the
series :)
Kyrill
Ok for stage1?
[gcc/]
2014-03-19 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64.md (rev16<mode>2): New pattern.
(rev16<mode>2_alt): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
(aarch_rev16_shleft_mask_imm_p): Likewise.
(aarch_rev16_p_1): Likewise.
(aarch_rev16_p): Likewise.
* config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
(aarch_rev16_shright_mask_imm_p): Likewise.
(aarch_rev16_shleft_mask_imm_p): Likewise.
[gcc/testsuite/]
2014-03-19 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/aarch64/rev16_1.c: New test.
