On Wed, Apr 2, 2014 at 12:04 PM, Jiong Wang <jiong.w...@arm.com> wrote: > > On 25/03/14 15:44, Richard Earnshaw wrote: >> >> On 24/03/14 11:26, Jiong Wang wrote: >>> >>> This patch enables tail call optimization for long call on arm. >>> >>> Previously we have too strict check on arm_function_ok_for_sibcall and >>> be lack of the support on sibcall/sibcall_value expand that long call >>> tail oppportunities are lost. >>> >>> OK for next next stage 1? >>> >> I think this is OK for EABI targets (since we can rely on the linker >> generating the right form of interworking veneer), but I'm less certain >> about other systems (do we still support COFF). >> >> I think I'd prefer the patch to factor in TARGET_AAPCS_BASED and to >> assume that if that is true then arbitrary tail-calls are safe. > > > Hi Richard, > > IMHO, this is actually a tail call optimization, we just need to make sure > the register which hold the address be caller saved then it will be OK. > > Updated the change log to fix that "aarch64" typo. No modification on the > patch, but enclose it in this reply to keep wholeness. > > So, is it ok for next stage-1? >
This is OK for stage1. Ramana > > Thanks. > > -- > Jiong > > > gcc/ > * config/arm/predicates.md (call_insn_operand): Add long_call check. > * config/arm/arm.md (sibcall, sibcall_value): Force the address to reg > for long_call. > * config/arm/arm.c (arm_function_ok_for_sibcall): Remove long_call > restriction. > > gcc/testsuite > gcc.target/arm/tail-long-call.c: New test.
