> -----Original Message-----
> From: Maciej W. Rozycki [mailto:ma...@codesourcery.com]
> Sent: Tuesday, April 15, 2014 7:28 AM
> To: Richard Sandiford
> Cc: Matthew Fortune; Moore, Catherine; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] [MIPS] Fix operands for microMIPS SW16, SH16 and
> SB16
>
> On Tue, 15 Apr 2014, Richard Sandiford wrote:
>
> > > I believe you need to adjust constraints to ensure constant 0 is
> > > known to produce a 16-bit instruction encoding where possible.
> > > Otherwise you'll end up with suboptimal code when the instruction is
> > > in a branch delay slot.
> >
> > Yeah, it'd be good to do that too (although this is a preexisting problem).
>
> Well, it depends on how you look at the problem being solved here -- if it is
> "for SW16, SH16 and SB16 GCC produces broken code for the `s0'
> source register", then indeed it is, whereas if it is "GCC does not handle the
> source register set for SW16, SH16 and SB16 correctly", then it is a part of
> the
> same problem, not completely corrected. I can live with that until 4.10/4.9.1
> though if you prefer.
>
> > I'm relying on you guys to do the microMIPS stuff though -- I don't
> > have a way of testing it.
>
> An assembly/objdump test is enough to cover this, so you've got all tools at
> hand, although I understand you may not be inclined to rush working on it. ;)
>
I'll take care of this bit.
