[PATCH], PR target/60876 -- fix build issue with powerpc

[Michael Meissner]

I committed the following patch as obvious to fix the PowerPC build issue that
came up with changes to machmode.h.  These changes allow the compiler to build
and bootstrap. Submitted as subversion id 209498.

2014-04-17  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        PR target/60876
        * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Make sure
        GET_MODE_SIZE gets passed an enum machine_mode type and not
        integer.
        (rs6000_init_hard_regno_mode_ok): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c  (revision 209494)
+++ gcc/config/rs6000/rs6000.c  (working copy)
@@ -2329,6 +2329,8 @@ rs6000_setup_reg_addr_masks (void)
 
   for (m = 0; m < NUM_MACHINE_MODES; ++m)
     {
+      enum machine_mode m2 = (enum machine_mode)m;
+
       /* SDmode is special in that we want to access it only via REG+REG
         addressing on power7 and above, since we want to use the LFIWZX and
         STFIWZX instructions to load it.  */
@@ -2363,13 +2365,13 @@ rs6000_setup_reg_addr_masks (void)
 
              if (TARGET_UPDATE
                  && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
-                 && GET_MODE_SIZE (m) <= 8
-                 && !VECTOR_MODE_P (m)
-                 && !COMPLEX_MODE_P (m)
+                 && GET_MODE_SIZE (m2) <= 8
+                 && !VECTOR_MODE_P (m2)
+                 && !COMPLEX_MODE_P (m2)
                  && !indexed_only_p
-                 && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8)
-                 && !(m == DFmode && TARGET_UPPER_REGS_DF)
-                 && !(m == SFmode && TARGET_UPPER_REGS_SF))
+                 && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8)
+                 && !(m2 == DFmode && TARGET_UPPER_REGS_DF)
+                 && !(m2 == SFmode && TARGET_UPPER_REGS_SF))
                {
                  addr_mask |= RELOAD_REG_PRE_INCDEC;
 
@@ -2815,6 +2817,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
 
       for (m = 0; m < NUM_MACHINE_MODES; ++m)
        {
+         enum machine_mode m2 = (enum machine_mode)m;
          int reg_size2 = reg_size;
 
          /* TFmode/TDmode always takes 2 registers, even in VSX.  */
@@ -2823,7 +2826,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
            reg_size2 = UNITS_PER_FP_WORD;
 
          rs6000_class_max_nregs[m][c]
-           = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2;
+           = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
        }
     }