On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon <christophe.l...@linaro.org> wrote: > On 27 February 2014 14:58, Ramana Radhakrishnan <ramra...@arm.com> wrote: >> Hi >> >> I noticed that for T32 we don't allow any old register for DImode values. >> The restriction of an even register is true only for ARM state because the >> ISA doesn't allow any old register in this place. In a few large .i files >> that I had knocking about, noticed a nice drop in stack usage and a >> generally improved register allocation strategy. >> >> Queued for stage1 after suitable testing including a bootstrap and >> regression test in Thumb2 found no issues. >> >> regards >> Ramana >> >> <DATE> Ramana Radhakrishnan <ramana.radhakrish...@arm.com> >> >> * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen restrictions on >> core registers for DImode values in Thumb2. >> > > Hi Ramana, > > I've noticed some regressions after this patch has been committed (rev > 209615): > > gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer > -funroll-all-loops -finline-functions > gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer -funroll-loops > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto > -fno-use-linker-plugin -flto-partition=none > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto > -fuse-linker-plugin -fno-fat-lto-objects
> Now all produce ICE in several GCC configurations (mostly when > generating thumb code) eg: > --target arm-none-eabi --with-cpu=cortex-a9 --with-mode=thumb > --target arm-none-linux-gnueabi --with-cpu=cortex-a9 --with-mode=thumb > Thanks for the report - I'll have a look. I've had this in a tree for testing for sometime that runs these configurations atleast the bare-metal arm-none-eabi one with multilib testing for thumb. > but it's OK for target arm-none-linux-gnueabihf. > > See > http://cbuild.validation.linaro.org/build/cross-validation/gcc/209615/report-build-info.html > > Christophe.
