Ping ... BR, Terry
> -----Original Message----- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Terry Guo > Sent: Friday, April 11, 2014 3:36 PM > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw; Ramana Radhakrishnan > Subject: [Patch, GCC/Thumb1] Improve 64bit constant load for Thumb1 > > Hi there, > > Current gcc prefers to using two LDR instructions to load 64bit constants. > This could miss some chances that 64bit load can be done in fewer > instructions or fewer cycles. For example, below code to load 0x100000001 > > mov r0, #1 > mov r1, #1 > > is better than current solution: > > ldr r1, .L2+4 > ldr r0, .L2 > .L2: > .word 1 > .word 1 > > The attached patch intends to split 64bit load to take advantage of such > chances. Tested with gcc regression test on cortex-m0. No new regressions. > > Is it ok to stage 1? > > BR, > Terry > > gcc/ > 2014-04-11 Terry Guo <terry....@arm.com> > > * config/arm/arm.md (split 64-bit constant for Thumb1): New split > pattern. > > gcc/testsuite/ > 2014-04-11 Terry Guo <terry....@arm.com> > > * gcc.target/arm/thumb1-load-64bit-constant-1.c: New test. > * gcc.target/arm/thumb1-load-64bit-constant-2.c: Ditto. > * gcc.target/arm/thumb1-load-64bit-constant-3.c: Ditto.