Compiling some applications with -mgeneral-regs-only produces better
code (runs faster) compared to not using it. The difference here is that
when -mgeneral-regs-only is not used, floating point register are also
used in register allocation. Then IRA/LRA has to move them to core
registers before performing operations.
I experimented with TARGET_SPILL_CLASS (as in attached patch) to make
floating point register class as just spill class for integer pseudos.
Though this benefits the application which had this issue. Overall
performance with speck2k is neutral (some of the benchmarks benefits a
lot but others regress). I am looking to see if I can make it perform
better overall. Any suggestions welcome.
Attached experimental patch passes regression but 168.wupwise and
187.facerec miscompares now. I am looking at fixing this as well.
Thanks,
Kugan
gcc/
2014-05-22 Kugan Vivekanandarajah <kug...@linaro.org>
* config/aarch64/aarch64.c (generic_regmove_cost) : Adjust GP2FP and
FP2GP costs.
(aarch64_spill_class) : New function.
(TARGET_SHIFT_TRUNCATION_MASK) : Define.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a3147ee..16d1b51 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -184,8 +184,8 @@ __extension__
static const struct cpu_regmove_cost generic_regmove_cost =
{
NAMED_PARAM (GP2GP, 1),
- NAMED_PARAM (GP2FP, 2),
- NAMED_PARAM (FP2GP, 2),
+ NAMED_PARAM (GP2FP, 5),
+ NAMED_PARAM (FP2GP, 5),
/* We currently do not provide direct support for TFmode Q->Q move.
Therefore we need to raise the cost above 2 in order to have
reload handle the situation. */
@@ -4882,6 +4882,18 @@ aarch64_register_move_cost (enum machine_mode mode
ATTRIBUTE_UNUSED,
return regmove_cost->FP2FP;
}
+/* Return class of registers which could be used for pseudo of MODE
+ and of class RCLASS for spilling instead of memory. */
+static reg_class_t
+aarch64_spill_class (reg_class_t rclass, enum machine_mode mode)
+{
+ if ((GET_MODE_CLASS (mode) == MODE_INT)
+ && reg_class_subset_p (rclass, GENERAL_REGS))
+ return FP_REGS;
+ return NO_REGS;
+}
+
+
static int
aarch64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
reg_class_t rclass ATTRIBUTE_UNUSED,
@@ -8431,6 +8443,9 @@ aarch64_cannot_change_mode_class (enum machine_mode from,
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
+#undef TARGET_SPILL_CLASS
+#define TARGET_SPILL_CLASS aarch64_spill_class
+
#undef TARGET_SHIFT_TRUNCATION_MASK
#define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
