On 06/01/2014 03:00 AM, Tom de Vries wrote:
> +aarch64_emit_call_insn (rtx pat)
> +{
> + rtx insn = emit_call_insn (pat);
> +
> + rtx *fusage = &CALL_INSN_FUNCTION_USAGE (insn);
> + clobber_reg (fusage, gen_rtx_REG (word_mode, IP0_REGNUM));
> + clobber_reg (fusage, gen_rtx_REG (word_mode, IP1_REGNUM));
Actually, I'd like to know more about how this is supposed to work.
Why are you only marking the two registers that would be used by a PLT entry,
but not those clobbered by the ld.so trampoline, or indeed the unknown function
that would be called from the PLT.
Oh, I see, looking at the code we do actually follow the cgraph and make sure
it is a direct call with a known destination. So, in fact, it's only the
registers that could be clobbered by ld branch islands (so these two are still
correct for aarch64).
This means the documentation is actually wrong when it mentions PLTs at all.
Do we in fact make sure this isn't an ifunc resolver? I don't immediately see
how those get wired up in the cgraph...
r~
