Hello,
This patch extends "vec_extract_hi_<mode>"
pattern to support AVX-512DQ insn.
Bootstrapped.
Bootstrapped.
New tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
* config/i386/i386.md
(define_attr "isa"): Add avx512dq, noavx512dq.
(define_attr "enabled"): Ditto.
* config/i386/sse.md
(define_insn "vec_extract_hi_<mode><mask_name>"): Support masking.
--
Thanks, K
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b8ce6c0..3a797c8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -741,7 +741,7 @@
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
- fma_avx512f,avx512bw,noavx512bw"
+ fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq"
(const_string "base"))
(define_attr "enabled" ""
@@ -774,6 +774,8 @@
(symbol_ref "TARGET_FMA || TARGET_AVX512F")
(eq_attr "isa" "avx512bw") (symbol_ref "TARGET_AVX512BW")
(eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
+ (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
+ (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
]
(const_int 1)))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 910b29b..3d3d1a0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -6132,6 +6132,29 @@
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "vec_extract_hi_<mode><mask_name>"
+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=<store_mask_constraint>,vm")
+ (vec_select:<ssehalfvecmode>
+ (match_operand:V16FI 1 "register_operand" "v,v")
+ (parallel [(const_int 8) (const_int 9)
+ (const_int 10) (const_int 11)
+ (const_int 12) (const_int 13)
+ (const_int 14) (const_int 15)])))]
+ "TARGET_AVX512F && (!<mask_applied> || TARGET_AVX512DQ)"
+ "@
+ vextract<shuffletype>32x8\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>,
%1, 0x1}
+ vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix_extra" "1")
+ (set_attr "isa" "avx512dq,noavx512dq")
+ (set_attr "length_immediate" "1")
+ (set (attr "memory")
+ (if_then_else (match_test "MEM_P (operands[0])")
+ (const_string "store")
+ (const_string "none")))
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_expand "avx_vextractf128<mode>"
[(match_operand:<ssehalfvecmode> 0 "nonimmediate_operand")
(match_operand:V_256 1 "register_operand")
@@ -6178,23 +6201,6 @@
DONE;
})
-(define_insn "vec_extract_hi_<mode>"
- [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m")
- (vec_select:<ssehalfvecmode>
- (match_operand:V16FI 1 "nonimmediate_operand" "v,v")
- (parallel [(const_int 8) (const_int 9)
- (const_int 10) (const_int 11)
- (const_int 12) (const_int 13)
- (const_int 14) (const_int 15)])))]
- "TARGET_AVX512F"
- "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}"
- [(set_attr "type" "sselog")
- (set_attr "prefix_extra" "1")
- (set_attr "length_immediate" "1")
- (set_attr "memory" "none,store")
- (set_attr "prefix" "evex")
- (set_attr "mode" "XI")])
-
(define_insn_and_split "vec_extract_lo_<mode>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=x,m")
(vec_select:<ssehalfvecmode>
