Hello Uroš, On 20 Aug 15:16, Uros Bizjak wrote: > OK with this change. I've discovered a problem with assembler operand of vshuf*64x2 insn.
Patch below bootstrapped and avx512-regtested. Is it ok for trunk? gcc/ * config/i386/sse.md (define_mode_attr concat_tg_mode): Move up. (define_insn "<mask_codefor>avx512dq_broadcast<mode><mask_name>_1"): Use `concat_tg_mode' attribute to determine asm register size. -- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fa23330..e1d42f8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -718,6 +718,11 @@ (V16SF "ss") (V8SF "ss") (V4SF "ss") (V8DF "sd") (V4DF "sd") (V2DF "sd")]) +;; Tight mode of assembler operand to mode iterator +(define_mode_attr concat_tg_mode + [(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t") + (V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")]) + ;; Include define_subst patterns for instructions with mask (include "subst.md") @@ -14702,7 +14708,7 @@ (match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))] "TARGET_AVX512DQ" "@ - vshuf<shuffletype>64x2\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0} + vshuf<shuffletype>64x2\t{$0x0, %<concat_tg_mode>1, %<concat_tg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<concat_tg_mode>1, %<concat_tg_mode>1, 0x0} vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") @@ -15448,11 +15454,6 @@ (set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseinsnmode>")]) -;; For avx_vec_concat<mode> insn pattern -(define_mode_attr concat_tg_mode - [(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t") - (V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")]) - (define_insn "avx_vec_concat<mode>" [(set (match_operand:V_256_512 0 "register_operand" "=x,x") (vec_concat:V_256_512