Hi all,Some intrinsics had the wrong name (inconsistent with the NEON intrinsics spec). This patch fixes that and adds the vrndx_f32 and vrndxq_f32 intrinsics that were missing. These map down to vrintx.f32 NEON instructions (d and q forms). We already had builtins defined for them, just the intrinsics were not wired up to them properly.
Tested arm-none-eabi Ok for trunk? 2014-09-23 Kyrylo Tkachov <kyrylo.tkac...@arm.com> * config/arm/arm_neon.h (vrndqn_f32): Rename to... (vrndnq_f32): ... this. (vrndqa_f32): Rename to... (vrndaq_f32): ... this. (vrndqp_f32): Rename to... (vrndpq_f32): ... this. (vrndqm_f32): Rename to... (vrndmq_f32): ... this. (vrndx_f32): New intrinsic. (vrndxq_f32): Likewise. 2014-09-23 Kyrylo Tkachov <kyrylo.tkac...@arm.com> * gcc.target/arm/simd/neon-vrndx_f32_1.c: New test. * gcc.target/arm/simd/neon-vrndxq_f32_1.c: Likewise. * gcc.target/arm/neon/vrndqaf32.c: Rename to... * gcc.target/arm/neon/vrndaqf32.c: ... This. Update intrinsic names. * gcc.target/arm/neon/vrndqmf32.c: Rename to... * gcc.target/arm/neon/vrndmqf32.c: ... This. Update intrinsic names. * gcc.target/arm/neon/vrndqnf32.c: Rename to... * gcc.target/arm/neon/vrndnqf32.c: ... This. Update intrinsic names. * gcc.target/arm/neon/vrndqpf32.c: Rename to... * gcc.target/arm/neon/vrndpqf32.c: ... This. Update intrinsic names.
commit cd1f0ff54922b48e1fd12446ddde694b65b5e932 Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com> Date: Thu Sep 11 10:38:22 2014 +0100 [ARM] Fix some rounding intrinsics diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 47f6c5e..e034f6b 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -1466,7 +1466,7 @@ vrndn_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqn_f32 (float32x4_t __a) +vrndnq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintnv4sf (__a); } @@ -1482,7 +1482,7 @@ vrnda_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqa_f32 (float32x4_t __a) +vrndaq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintav4sf (__a); } @@ -1498,7 +1498,7 @@ vrndp_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqp_f32 (float32x4_t __a) +vrndpq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintpv4sf (__a); } @@ -1514,12 +1514,31 @@ vrndm_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqm_f32 (float32x4_t __a) +vrndmq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintmv4sf (__a); } #endif + +#if __ARM_ARCH >= 8 +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrndx_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vrintxv2sf (__a); +} + +#endif + +#if __ARM_ARCH >= 8 +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrndxq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vrintxv4sf (__a); +} + +#endif + #if __ARM_ARCH >= 8 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vrnd_f32 (float32x2_t __a) diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c new file mode 100644 index 0000000..c1acb64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndaq_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndaqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndaq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c new file mode 100644 index 0000000..306d4f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndmq_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndmqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndmq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c new file mode 100644 index 0000000..0a70529 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndnq_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndnqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndnq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c new file mode 100644 index 0000000..723fee4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c @@ -0,0 +1,20 @@ +/* Test the `vrndpq_f32' ARM Neon intrinsic. */ +/* This file was autogenerated by neon-testgen. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O0" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +void test_vrndpqf32 (void) +{ + float32x4_t out_float32x4_t; + float32x4_t arg0_float32x4_t; + + out_float32x4_t = vrndpq_f32 (arg0_float32x4_t); +} + +/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c deleted file mode 100644 index b7b5d73..0000000 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Test the `vrndqaf32' ARM Neon intrinsic. */ -/* This file was autogenerated by neon-testgen. */ - -/* { dg-do assemble } */ -/* { dg-require-effective-target arm_v8_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ -/* { dg-add-options arm_v8_neon } */ - -#include "arm_neon.h" - -void test_vrndqaf32 (void) -{ - float32x4_t out_float32x4_t; - float32x4_t arg0_float32x4_t; - - out_float32x4_t = vrndqa_f32 (arg0_float32x4_t); -} - -/* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c deleted file mode 100644 index 6d16bfc..0000000 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Test the `vrndqmf32' ARM Neon intrinsic. */ -/* This file was autogenerated by neon-testgen. */ - -/* { dg-do assemble } */ -/* { dg-require-effective-target arm_v8_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ -/* { dg-add-options arm_v8_neon } */ - -#include "arm_neon.h" - -void test_vrndqmf32 (void) -{ - float32x4_t out_float32x4_t; - float32x4_t arg0_float32x4_t; - - out_float32x4_t = vrndqm_f32 (arg0_float32x4_t); -} - -/* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c deleted file mode 100644 index b31ca95..0000000 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Test the `vrndqnf32' ARM Neon intrinsic. */ -/* This file was autogenerated by neon-testgen. */ - -/* { dg-do assemble } */ -/* { dg-require-effective-target arm_v8_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ -/* { dg-add-options arm_v8_neon } */ - -#include "arm_neon.h" - -void test_vrndqnf32 (void) -{ - float32x4_t out_float32x4_t; - float32x4_t arg0_float32x4_t; - - out_float32x4_t = vrndqn_f32 (arg0_float32x4_t); -} - -/* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c deleted file mode 100644 index 5c4a866..0000000 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Test the `vrndqpf32' ARM Neon intrinsic. */ -/* This file was autogenerated by neon-testgen. */ - -/* { dg-do assemble } */ -/* { dg-require-effective-target arm_v8_neon_ok } */ -/* { dg-options "-save-temps -O0" } */ -/* { dg-add-options arm_v8_neon } */ - -#include "arm_neon.h" - -void test_vrndqpf32 (void) -{ - float32x4_t out_float32x4_t; - float32x4_t arg0_float32x4_t; - - out_float32x4_t = vrndqp_f32 (arg0_float32x4_t); -} - -/* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ -/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c new file mode 100644 index 0000000..3d2f27f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndx_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x2_t +test_vrndx_f32 (float32x2_t in) +{ + return vrndx_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c new file mode 100644 index 0000000..c89cb24 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndxq_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x4_t +test_vrndxq_f32 (float32x4_t in) +{ + return vrndxq_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */