Hi all
we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 216130 as r216256. We have also backported this set of revisions:
r209643 as 215975 : [AArch64] Define TARGET_FLAGS_REGNUM
r211881 as 215975 : PR target/61565
r213035 as 215846 : [AArch64] libitm: Improve _ITM_beginTransaction
r213090 as 215847 : [AArch64] Fix *extr_insv_lower_reg<mode> pattern
r214824 as 215977 : [AArch64] Use CC_Z and CC_NZ with csinc and
similar instructions
r214825 as 216007 : [AArch32][1/2] Implement lceil, lfloor, lround
optabs with new ARMv8-A instructions
r214826 as 216007 : [AArch32][2/2] Vectorise lroundf, lfloorf, lceilf
using the new ARMv8-A vcvt* instructions
r214886 as 215944 : [AArch64] Improve epilogue unwind info rth
r214940 as 215853 : [AArch64] Add a mode to operand 1 of sibcall_value_insn
r214943 as 215946 : [AArch64] Add a builtin for rbit(q?)_p8; add
intrinsics and tests.
r214944 as 215948 : [AArch32/AArch64] Schedule alu_ext for Cortex-A53
r214945 as 215949 : [AArch64] Remove varargs from aarch64_simd_expand_args
r214947 as 215854 : [AArch64] Tidy: remove unused qualifier_const_pointer
r214959 as 215857 : [AArch32/AArch64] Add scheduling info for ARMv8-A
FPU new instructions in Cortex-A53
r215050 as 215858 : [AArch32[1/7] Convert FP mnemonics to UAL | mov patterns.
r215051 as 215858 : [AArch32][2/7] Convert FP mnemonics to UAL |
add/sub/div/abs patterns
r215052 as 215858 : [AARch32][3/7] Convert FP mnemonics to UAL |
mul+add patterns
r215053 as 215858 : [AArch32][4/7] Convert FP mnemonics to UAL | vcvt patterns
r215054 as 215858 : [AArch32][5/7] Convert FP mnemonics to UAL | sqrt
and FP compare patterns
r215055 as 215858 : [AArch32][6/7] Convert FP mnemonics to UAL |
movcc_vfp (fmstat)
r215056 as 215858 : [AArch32][7/7] Convert FP mnemonics to UAL |
f{ld,st}m -> v{ld,st}m
r215067 as 215923 : [AArch32] Enable auto-vectorization for copysignf
r215085 as 216007 : [AArch32][tests] Make input and output arrays
128-bit aligned in vectorisation tests
r215086 as 215928 : [AARch64] Add crtfastmath for AArch64
r215101 as 215929 : PR target/56846 libstdc++
r215136 as 215932 : PR target/63209
r215205 as 215935 : [Ree] Ensure inserted copy don't change the number
of hard registers
r215260 as 215937 : [AArch64] Fix force_simd macro in vdup_lane_2
r215321 as 215938 : Disallow -mfpu=neon for unsuitable architectures
r215346 as 215940 : movmisalign<mode>_neon_load
r215385 as 215941 : [AArch64] Add constraint letter for
stack_protect_test pattern
r215471 as 216004 : [AArch64] Auto-generate the "BUILTIN_" macros
This will be part of our 2014.10 4.9 release.
Thanks,
Yvan
