Hello,
On 20 Oct 14:36, Jakub Jelinek wrote:
> On Tue, Oct 14, 2014 at 11:18:28AM +0400, Kirill Yukhin wrote:
> > * config/i386/sse.md (define_mode_iterator VI_AVX2): Extend
> > to support AVX-512BW.
> > (define_mode_iterator VI124_AVX2_48_AVX512F): Remove.
> > (define_expand "<plusminus_insn><mode>3"): Remove masking support.
> > (define_insn "*<plusminus_insn><mode>3"): Ditto.
> > (define_expand "<plusminus_insn><VI48_AVX512VL:mode>3_mask"): New.
> > (define_expand "<plusminus_insn><VI12_AVX512VL:mode>3_mask"): Ditto.
> > (define_insn "*<plusminus_insn><VI48_AVX512VL:mode>3_mask"): Ditto.
> > (define_insn "*<plusminus_insn><VI12_AVX512VL:mode>3_mask"): Ditto.
> > (define_expand "<sse2_avx2>_andnot<mode>3"): Remove masking support.
> > (define_insn "*andnot<mode>3"): Ditto.
> > (define_expand "<sse2_avx2>_andnot<VI48_AVX512VL:mode>3_mask"): New.
> > (define_expand "<sse2_avx2>_andnot<VI12_AVX512VL:mode>3_mask"): Ditto.
> > (define_insn "*andnot<VI48_AVX512VL:mode>3<mask_name>"): Ditto.
> > (define_insn "*andnot<VI12_AVX512VL:mode>3<mask_name>"): Ditto.
> > (define_insn "*abs<mode>2"): Remove masking support.
> > (define_insn "abs<VI48_AVX512VL:mode>2_mask"): New.
> > (define_insn "abs<VI12_AVX512VL:mode>2_mask"): Ditto.
> > (define_expand "abs<mode>2"): Use VI_AVX2 mode iterator.
>
> Unfortunately this caused PR63600. The problem is that VI_AVX2
> mode iterator includes V2DI and for AVX2 also V4DI, but for pre-ssse3
> ix86_expand_sse2_abs doesn't handle V2DI (and can't easily, we don't have
> PSRAQ instruction), for ssse3 there is no vpabsq instruction, and for
> avx2 neither.
> We can handle V2DI/V4DI only for TARGET_AVX512VL, and V8DI for
> TARGET_AVX512F.
> Thus, IMHO the mode iterator on at least
> (define_insn "*abs<mode>2"
> and on
> (define_expand "abs<mode>2"
> is wrong, should not include V2DI/V4DI unless TARGET_AVX512VL
> (so new (or ressurrected, was that VI124_AVX2_48_AVX512F?)
> specialized mode iterator?).
This patch removes absq insn patterns for non-AVX-512 targets.
gcc/
* config/i386/sse.md (define_mode_iterator VI_AVX2): Restore to 128-,
256- bit integer modes only.
(define_mode_iterator VI_AVX2_AVX512): New.
(define_expand "neg<mode>2"): Use VI_AVX2_AVX512 mode iterator.
(define_expand "<plusminus_insn><mode>3"): Ditto.
(define_insn "*<plusminus_insn><mode>3"): Ditto.
(define_expand "<sse2_avx2>_andnot<mode>3"): Ditto.
(define_mode_iterator VI1248_AVX512VL_AVX512BW): New.
(define_insn "abs<VI1248_AVX512VL_AVX512BW:mode>2"): Ditto.
Bootstrap in progress. AVX-512 tests pass.
Is it ok for trunk?
--
Thanks, K
AVX-512. Disable absq for non AVX-512 targets.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index fd40623..74aca48 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -271,6 +271,11 @@
(V4DI "TARGET_AVX") V2DI])
(define_mode_iterator VI_AVX2
+ [(V32QI "TARGET_AVX2") V16QI
+ (V16HI "TARGET_AVX2") V8HI
+ (V8SI "TARGET_AVX2") V4SI])
+
+(define_mode_iterator VI_AVX2_AVX512
[(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI
(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI
(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI
@@ -9142,18 +9147,18 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "neg<mode>2"
- [(set (match_operand:VI_AVX2 0 "register_operand")
- (minus:VI_AVX2
+ [(set (match_operand:VI_AVX2_AVX512 0 "register_operand")
+ (minus:VI_AVX2_AVX512
(match_dup 2)
- (match_operand:VI_AVX2 1 "nonimmediate_operand")))]
+ (match_operand:VI_AVX2_AVX512 1 "nonimmediate_operand")))]
"TARGET_SSE2"
"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand")
- (plusminus:VI_AVX2
- (match_operand:VI_AVX2 1 "nonimmediate_operand")
- (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
+ [(set (match_operand:VI_AVX2_AVX512 0 "register_operand")
+ (plusminus:VI_AVX2_AVX512
+ (match_operand:VI_AVX2_AVX512 1 "nonimmediate_operand")
+ (match_operand:VI_AVX2_AVX512 2 "nonimmediate_operand")))]
"TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
@@ -9180,10 +9185,10 @@
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*<plusminus_insn><mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v")
- (plusminus:VI_AVX2
- (match_operand:VI_AVX2 1 "nonimmediate_operand" "<comm>0,v")
- (match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,vm")))]
+ [(set (match_operand:VI_AVX2_AVX512 0 "register_operand" "=x,v")
+ (plusminus:VI_AVX2_AVX512
+ (match_operand:VI_AVX2_AVX512 1 "nonimmediate_operand" "<comm>0,v")
+ (match_operand:VI_AVX2_AVX512 2 "nonimmediate_operand" "xm,vm")))]
"TARGET_SSE2
&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"@
@@ -10715,10 +10720,10 @@
})
(define_expand "<sse2_avx2>_andnot<mode>3"
- [(set (match_operand:VI_AVX2 0 "register_operand")
- (and:VI_AVX2
- (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand"))
- (match_operand:VI_AVX2 2 "nonimmediate_operand")))]
+ [(set (match_operand:VI_AVX2_AVX512 0 "register_operand")
+ (and:VI_AVX2_AVX512
+ (not:VI_AVX2_AVX512 (match_operand:VI_AVX2_AVX512 1
"register_operand"))
+ (match_operand:VI_AVX2_AVX512 2 "nonimmediate_operand")))]
"TARGET_SSE2")
(define_expand "<sse2_avx2>_andnot<mode>3_mask"
@@ -13836,6 +13841,20 @@
}
})
+(define_mode_iterator VI1248_AVX512VL_AVX512BW
+ [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")
+ V16SI (V64QI "TARGET_AVX512BW") (V32HI "TARGET_AVX512BW")])
+
+(define_insn "abs<mode>2"
+ [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=v")
+ (abs:VI1248_AVX512VL_AVX512BW
+ (match_operand:VI1248_AVX512VL_AVX512BW 1 "nonimmediate_operand"
"vm")))]
+ "TARGET_AVX512F"
+ "vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
+ [(set_attr "type" "sselog1")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "abs<mode>2"
[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
(abs:MMXMODEI
