Bootstrapped and check-gcc on x86_64-none-linux-gnu.
gcc/ChangeLog:
* config/i386/i386.c (ix86_expand_reduc): Extract result into scalar.
* config/i386/sse.md (reduc_splus_v8df, reduc_<code>_<mode> * 3,
reduc_umin_v8hi): Rename to...
(reduc_plus_scal_v8df, reduc_<code>_scal_<mode> * 3,
reduc_umin_scal_v8hi): ...these, changing result mode to scalar.
(reduc_splus_v4df, reduc_splus_v2df, reduc_splus_v16sf,
reduc_splus_v8sf, reduc_splus_v4sf): Rename to...
(reduc_plus_scal_v4df, reduc_plus_scal_v2df, reduc_plus_scal_v16sf,
reduc_plus_scal_v8sf, reduc_plus_scal_v4sf): ...these, adding
gen_vec_extract for scalar result.commit 80b0d10a78b2f3e86325f373e99e9cf71e42e622
Author: Alan Lawrence <alan.lawre...@arm.com>
Date: Tue Oct 7 13:25:08 2014 +0100
i386
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4c4a6eb..670a5f5 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -41211,12 +41211,12 @@ emit_reduc_half (rtx dest, rtx src, int i)
}
/* Expand a vector reduction. FN is the binary pattern to reduce;
- DEST is the destination; IN is the input vector. */
+ DEST is the (scalar) destination; IN is the input vector. */
void
ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
{
- rtx half, dst, vec = in;
+ rtx half, dst = NULL_RTX, vec = in;
enum machine_mode mode = GET_MODE (in);
int i;
@@ -41225,23 +41225,21 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
&& mode == V8HImode
&& fn == gen_uminv8hi3)
{
- emit_insn (gen_sse4_1_phminposuw (dest, in));
- return;
+ dst = gen_reg_rtx (mode);
+ emit_insn (gen_sse4_1_phminposuw (dst, in));
}
-
- for (i = GET_MODE_BITSIZE (mode);
- i > GET_MODE_BITSIZE (GET_MODE_INNER (mode));
- i >>= 1)
- {
+ else
+ for (i = GET_MODE_BITSIZE (mode);
+ i > GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+ i >>= 1)
+ {
half = gen_reg_rtx (mode);
emit_reduc_half (half, vec, i);
- if (i == GET_MODE_BITSIZE (GET_MODE_INNER (mode)) * 2)
- dst = dest;
- else
- dst = gen_reg_rtx (mode);
+ dst = gen_reg_rtx (mode);
emit_insn (fn (dst, half, vec));
vec = dst;
}
+ ix86_expand_vector_extract (false, dest, dst, 0);
}
/* Target hook for scalar_mode_supported_p. */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7646d7..e4e0b95 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2238,8 +2238,8 @@
(set_attr "prefix_rep" "1,*")
(set_attr "mode" "V4SF")])
-(define_expand "reduc_splus_v8df"
- [(match_operand:V8DF 0 "register_operand")
+(define_expand "reduc_plus_scal_v8df"
+ [(match_operand:DF 0 "register_operand")
(match_operand:V8DF 1 "register_operand")]
"TARGET_AVX512F"
{
@@ -2247,30 +2247,35 @@
DONE;
})
-(define_expand "reduc_splus_v4df"
- [(match_operand:V4DF 0 "register_operand")
+(define_expand "reduc_plus_scal_v4df"
+ [(match_operand:DF 0 "register_operand")
(match_operand:V4DF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V4DFmode);
rtx tmp2 = gen_reg_rtx (V4DFmode);
+ rtx tmp3 = gen_reg_rtx (V4DFmode);
+
emit_insn (gen_avx_haddv4df3 (tmp, operands[1], operands[1]));
emit_insn (gen_avx_vperm2f128v4df3 (tmp2, tmp, tmp, GEN_INT (1)));
- emit_insn (gen_addv4df3 (operands[0], tmp, tmp2));
+ emit_insn (gen_addv4df3 (tmp3, tmp, tmp2));
+ emit_insn (gen_vec_extractv4df (operands[0], tmp3, GEN_INT (1)));
DONE;
})
-(define_expand "reduc_splus_v2df"
- [(match_operand:V2DF 0 "register_operand")
+(define_expand "reduc_plus_scal_v2df"
+ [(match_operand:DF 0 "register_operand")
(match_operand:V2DF 1 "register_operand")]
"TARGET_SSE3"
{
- emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
+ rtx tmp = gen_reg_rtx (V2DFmode);
+ emit_insn (gen_sse3_haddv2df3 (tmp, operands[1], operands[1]));
+ emit_insn (gen_vec_extractv2df (operands[0], tmp, GEN_INT (0)));
DONE;
})
-(define_expand "reduc_splus_v16sf"
- [(match_operand:V16SF 0 "register_operand")
+(define_expand "reduc_plus_scal_v16sf"
+ [(match_operand:SF 0 "register_operand")
(match_operand:V16SF 1 "register_operand")]
"TARGET_AVX512F"
{
@@ -2278,30 +2283,35 @@
DONE;
})
-(define_expand "reduc_splus_v8sf"
- [(match_operand:V8SF 0 "register_operand")
+(define_expand "reduc_plus_scal_v8sf"
+ [(match_operand:SF 0 "register_operand")
(match_operand:V8SF 1 "register_operand")]
"TARGET_AVX"
{
rtx tmp = gen_reg_rtx (V8SFmode);
rtx tmp2 = gen_reg_rtx (V8SFmode);
+ rtx tmp3 = gen_reg_rtx (V8SFmode);
+
emit_insn (gen_avx_haddv8sf3 (tmp, operands[1], operands[1]));
emit_insn (gen_avx_haddv8sf3 (tmp2, tmp, tmp));
emit_insn (gen_avx_vperm2f128v8sf3 (tmp, tmp2, tmp2, GEN_INT (1)));
- emit_insn (gen_addv8sf3 (operands[0], tmp, tmp2));
+ emit_insn (gen_addv8sf3 (tmp3, tmp, tmp2));
+ emit_insn (gen_vec_extractv8sf (operands[0], tmp3, GEN_INT (0)));
DONE;
})
-(define_expand "reduc_splus_v4sf"
- [(match_operand:V4SF 0 "register_operand")
+(define_expand "reduc_plus_scal_v4sf"
+ [(match_operand:SF 0 "register_operand")
(match_operand:V4SF 1 "register_operand")]
"TARGET_SSE"
{
if (TARGET_SSE3)
{
rtx tmp = gen_reg_rtx (V4SFmode);
+ rtx tmp2 = gen_reg_rtx (V4SFmode);
emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
- emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp));
+ emit_insn (gen_sse3_haddv4sf3 (tmp2, tmp, tmp));
+ emit_insn (gen_vec_extractv4sf (operands[0], tmp2, GEN_INT (0)));
}
else
ix86_expand_reduc (gen_addv4sf3, operands[0], operands[1]);
@@ -2317,9 +2327,9 @@
(V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
(V8DF "TARGET_AVX512F")])
-(define_expand "reduc_<code>_<mode>"
+(define_expand "reduc_<code>_scal_<mode>"
[(smaxmin:REDUC_SMINMAX_MODE
- (match_operand:REDUC_SMINMAX_MODE 0 "register_operand")
+ (match_operand:<ssescalarmode> 0 "register_operand")
(match_operand:REDUC_SMINMAX_MODE 1 "register_operand"))]
""
{
@@ -2327,9 +2337,9 @@
DONE;
})
-(define_expand "reduc_<code>_<mode>"
+(define_expand "reduc_<code>_scal_<mode>"
[(umaxmin:VI48_512
- (match_operand:VI48_512 0 "register_operand")
+ (match_operand:<ssescalarmode> 0 "register_operand")
(match_operand:VI48_512 1 "register_operand"))]
"TARGET_AVX512F"
{
@@ -2337,9 +2347,9 @@
DONE;
})
-(define_expand "reduc_<code>_<mode>"
+(define_expand "reduc_<code>_scal_<mode>"
[(umaxmin:VI_256
- (match_operand:VI_256 0 "register_operand")
+ (match_operand:<ssescalarmode> 0 "register_operand")
(match_operand:VI_256 1 "register_operand"))]
"TARGET_AVX2"
{
@@ -2347,9 +2357,9 @@
DONE;
})
-(define_expand "reduc_umin_v8hi"
+(define_expand "reduc_umin_scal_v8hi"
[(umin:V8HI
- (match_operand:V8HI 0 "register_operand")
+ (match_operand:HI 0 "register_operand")
(match_operand:V8HI 1 "register_operand"))]
"TARGET_SSE4_1"
{
