A slight oversight. and<mode>3_imm is predicated by rs6000_gen_cell_microcode
so we had better not generate it otherwise; and in that case, we need to force
the constant to a register.
Bootstrap and testsuite run are fine (of course, since this isn't
tested at all); comparing testsuite runs between -mcpu=cell and
default shows a few thousand fails (mainly ICEs in dfp), and no
differences between with and without this patch.
But this PR was a failure in Linux kernel build; I checked it did fail
to build without this patch, and works with (I built cell_defconfig).
Okay for trunk?
Segher
2014-11-27 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
PR target/64093
* config/rs6000/rs6000.md (and<mode>3): Don't generate
and<mode>3_imm unless rs6000_gen_cell_microcode is true.
---
gcc/config/rs6000/rs6000.md | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c8c3a68..f3b5aae 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2646,8 +2646,13 @@ (define_expand "and<mode>3"
if (logical_const_operand (operands[2], <MODE>mode)
&& !any_mask_operand (operands[2], <MODE>mode))
{
- emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
- DONE;
+ if (rs6000_gen_cell_microcode)
+ {
+ emit_insn (gen_and<mode>3_imm (operands[0], operands[1],
operands[2]));
+ DONE;
+ }
+ else
+ operands[2] = force_reg (<MODE>mode, operands[2]);
}
if ((<MODE>mode == DImode && !and64_2_operand (operands[2], <MODE>mode))
--
1.8.1.4
