On Mon, Dec 1, 2014 at 5:48 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > in my change on November 24th (adding the support to use scalar floating point > values in Altivec registers) there was a regression when Spec 2000 was > compiled > for 32-bit big endian power7 systems. The rs6000_legitimize_reload_address > function generated reg+offset address for scalar values. This resulted in > compiler generating these addresses to load up a constant in some cases in > 32-bit. This patch does not give an optimized address for scalar types if > they > can go in Altivec registers. By not generating an 'optimized' address, reload > falls to try other options, and it eventually generates the lfd instruction > with an offset instead of an lxsdx. > > I have bootstraped these patches on big endian power7, big endian power8, and > little endian power8 systems, and there were no regressions. Is the patch ok > to install? > > [gcc] > 2014-12-01 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/64019 > * config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Do > not create LO_SUM address for constant addresses if the type can > go in Altivec registers. > > [gcc/testsuite] > 2014-12-01 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/64019 > * gcc.target/powerpc/pr64019.c: New file.
Okay. Thanks, David
