On Thu, Dec 04, 2014 at 02:49:56PM -0600, Segher Boessenkool wrote:
> On Thu, Dec 04, 2014 at 04:43:34PM +0800, Zhenqiang Chen wrote:
> > C code:
> >
> > if (!--*p)
> >
> > rtl code:
> >
> > 6: r91:SI=[r90:SI]
> > 7: {r88:SI=r91:SI-0x1;clobber flags:CC;}
> > 8: [r90:SI]=r88:SI
> > 9: flags:CCZ=cmp(r88:SI,0)
> >
> > expected output:
> >
> > 8: {flags:CCZ=cmp([r90:SI]-0x1,0);[r90:SI]=[r90:SI]-0x1;}
> >
> > in assemble, it is
> >
> > decl (%eax)
>
> Combine does not consider combining 9 into 7 because there is no LOG_LINK
> between them (the link for r88 is between 8 and 7 already).
So combine tries to combine 6+7+8; the RTL it comes up with is a parallel
of the memory decrement (without cc clobber, but that is fine), and setting
r88 to the mem minus one. There is no such pattern in the target, and
combine cannot break the parallel into two sets (because the first modifies
the mem used by the second), so 6+7+8 doesn't combine.
Adding a bridge pattern in the target would work; or you can enhance combine
so it can break up this parallel correctly.
Segher
