This means we do not allow GPR0 as base address of those anymore. The
alternative is to not allow the carry bit to be live over any lo_sum,
which is more expensive.
2014-12-08 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
PR target/64180
* config/rs6000/darwin.md (macho_low_si): Remove "r" alternative.
(macho_low_di): Ditto.
* config/rs6000/rs6000.md (*largetoc_low): Ditto.
(tocref<mode>): Ditto.
(elf_low): Ditto.
* config/rs6000/spe.md (mov_si<mode>_e500_subreg0_elf_low_be): Ditto.
(mov_si<mode>_e500_subreg0_elf_low_le): Ditto.
(mov_si<mode>_e500_subreg4_elf_low_be): Ditto. Reformat condition.
(mov_si<mode>_e500_subreg4_elf_low_le): Ditto.
---
gcc/config/rs6000/darwin.md | 16 ++++++----------
gcc/config/rs6000/rs6000.md | 18 +++++++-----------
gcc/config/rs6000/spe.md | 18 +++++++++---------
3 files changed, 22 insertions(+), 30 deletions(-)
diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md
index 8b816b7..764f847 100644
--- a/gcc/config/rs6000/darwin.md
+++ b/gcc/config/rs6000/darwin.md
@@ -213,22 +213,18 @@ (define_expand "macho_low"
})
(define_insn "macho_low_si"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT"
- "@
- la %0,lo16(%2)(%1)
- addic %0,%1,lo16(%2)")
+ "la %0,lo16(%2)(%1)")
(define_insn "macho_low_di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"TARGET_MACHO && TARGET_64BIT"
- "@
- la %0,lo16(%2)(%1)
- addic %0,%1,lo16(%2)")
+ "la %0,lo16(%2)(%1)")
(define_split
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f3b5aae..abf20c3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -10712,13 +10712,11 @@ (define_insn "*largetoc_high_plus_aix<mode>"
"addis %0,%1+%3@u(%2)")
(define_insn "*largetoc_low"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(match_operand:DI 2 "" "")))]
"TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
- "@
- addi %0,%1,%2@l
- addic %0,%1,%2@l")
+ "addi %0,%1,%2@l")
(define_insn "*largetoc_low_aix<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
@@ -10728,7 +10726,7 @@ (define_insn "*largetoc_low_aix<mode>"
"la %0,%2@l(%1)")
(define_insn_and_split "*tocref<mode>"
- [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
+ [(set (match_operand:P 0 "gpc_reg_operand" "=b")
(match_operand:P 1 "small_toc_ref" "R"))]
"TARGET_TOC"
"la %0,%a1"
@@ -10747,13 +10745,11 @@ (define_insn "elf_high"
"lis %0,%1@ha")
(define_insn "elf_low"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"TARGET_ELF && ! TARGET_64BIT"
- "@
- la %0,%2@l(%1)
- addic %0,%1,%K2")
+ "la %0,%2@l(%1)")
;; Call and call_value insns
(define_expand "call"
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 8eec7b7..07c293c 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -2519,7 +2519,7 @@ (define_insn "*mov_si<mode>_e500_subreg0_le"
(define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
@@ -2538,13 +2538,13 @@ (define_insn_and_split
"*mov_si<mode>_e500_subreg0_elf_low_be"
(define_insn "*mov_si<mode>_e500_subreg0_elf_low_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 0)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
&& TARGET_ELF && !TARGET_64BIT)"
- "addic %0,%1,%K2")
+ "addi %0,%1,%K2")
;; ??? Could use evstwwe for memory stores in some cases, depending on
;; the offset.
@@ -2592,17 +2592,17 @@ (define_insn "mov_si<mode>_e500_subreg4_le"
(define_insn "*mov_si<mode>_e500_subreg4_elf_low_be"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"WORDS_BIG_ENDIAN
- && (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
- || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
- && TARGET_ELF && !TARGET_64BIT)"
- "addic %0,%1,%K2")
+ && ((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
+ || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
+ && TARGET_ELF && !TARGET_64BIT"
+ "addi %0,%1,%K2")
(define_insn_and_split "*mov_si<mode>_e500_subreg4_elf_low_le"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
- (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand 2 "" "")))]
"!WORDS_BIG_ENDIAN
&& (((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
--
1.8.1.4
