Le vendredi 07 avril 2006 à 02:54 -0500, Aaron W. LaFramboise a écrit : > I have also recently become interested in a GCC port for the 18F. > > Can someone summarize who--if anyone--is working on this, how much > progress he has made so far (Is his work based on mainline?), and any > expected future milestones? I am studying the gcc internal guide for the moment. I am very busy for the moment, and I won't write much code before July.
> > (And who are all of the people in the CC list? Is there some other list > discussing this?) I am on gcc dicussing list. > > I think that the major work that will need to be done for this port is > figuring out how to get segmentation to work. Some other potential > ports need this too, so if there's any way to do this in a way that all > ports can benefit, that would be great. I think this is definitely > possible, but it seems like it may take some effort--particularly to get > the changes into a form acceptable for inclusion into FSF GCC. I think so. Microchip have done a modified version of GCC-3.3 with DSPICs support, so we have got a heavy good base to work on the instruction set, wich is similar for PIC18. DSPIC is a 16 bit CPU, so is memory isn't segmented. > > The way I would do this (and will, perhaps, if noone else intends to > work on this any time soon) is to consider the access bank (low 128 GPRs > and some of the high 128 SPRs) as the GCC registers. (I am not sure if > ~140 registers is too many for GCC to handle effectively; Are there > ports that use this many?) This will yield a port that can deal with at > least 512 bytes of memory, I think. Implementing segmentation will give > it access to the rest of the banks. > For the instant, I don't know how to implement any kind of way in gcc. Salutations, Francois Poulain
