Hello!
I'm particularly interested in this patch
(http://gcc.gnu.org/ml/gcc-patches/2005-07/msg01128.html); pretty
nice for
users of Pentium 3 and Athlon. Has it been or will it be integrated into
mainline?
This patch heavily depends on the functionality of optimize mode
switching pass. Unfortunatelly, there is currently no way to tell
optimize_mode_switching() which modes are exclusive. Due to the way how
the emms switching patch was designed, it expects that either MMX or X87
mode can be active at once, to properly switch between x87 and MMX
registers.
PR target/19161 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19161)
comment #17 has an example of the control flow that can block both
register sets at once. Otherwise, the patch works as expected.
Uros.
